Method for forming a transistor for reducing a channel length

1. A method for forming a transistor, comprising:

forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate;

forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern;

forming an amorphous region at a lower part of both sidewalls of the gate polysilicon layer pattern;

reducing a channel length by removing the amorphous region so as to form a notch at a lower part of both sidewalls of the gate polysilicon layer pattern;

forming a gate spacer at both sidewalls of the gate polysilicon layer pattern; and

forming a high energy ion implantation region by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern and gate spacer.

2. The method of claim 1 , wherein the forming of the gate oxide layer pattern and gate polysilicon layer pattern comprises:

forming a gate oxide layer and gate polysilicon layer on the silicon substrate; and

patterning the gate oxide layer and gate polysilicon layer.

3. The method of claim 1 , wherein the forming an amorphous region includes forming the amorphous region together while forming a pocket ion implantation region below the low energy ion implantation region.

4. An apparatus for forming a transistor, comprising:

means for forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate;

means for forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern;

means for forming an amorphous region at a lower part of both sidewalls of the gate polysilicon layer pattern;

means for reducing a channel length by removing the amorphous region so as to form a notch at a lower part of both sidewalls of the gate polysilicon layer pattern;

means for forming a gate spacer at both sidewalls of the gate polysilicon layer pattern; and

means for forming a high energy ion implantation region by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern and gate spacer.

5. The apparatus of claim 4 , wherein the means for forming of the gate oxide layer pattern and gate polysilicon layer pattern comprises:

means for forming a gate oxide layer and gate polysilicon layer on the silicon substrate; and

means for patterning the gate oxide layer and gate polysilicon layer.

6. The apparatus of claim 4 , wherein means for the forming an amorphous region includes means for forming the amorphous region together while forming a pocket ion implantation region below the low energy ion implantation region.