IP Library Granted Patent US 7,482,692
Granted Patent B2
US 7,482,692 · App. 11/320,698 · Granted Jan 27, 2009

Tungsten plug structure of semiconductor device and method for forming the same

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Quick Facts
Patent No.
US 7,482,692
App. No.
11/320,698
Granted
Jan 27, 2009
Kind
B2
Abstract

A tungsten plug structure of a semiconductor device wherein a method for forming the same is performed at least twice to form a tungsten plug having a low aspect ratio, thereby obtaining an overlap margin between the tungsten plug and a metal line and minimizing contact resistance between the tungsten plug and a lower metal line layer. The plug structure of a semiconductor device includes a silicon substrate in which various elements for the semiconductor device are formed, a first dielectric film formed on the silicon substrate, having a first contact hole, a first plug buried in the first contact hole of the first dielectric film, having a low aspect ratio, a second dielectric film formed on an entire surface including the first dielectric film, having a second contact hole on the first plug, a second plug buried in the second contact hole of the second dielectric film, having a low aspect ratio, and a metal line formed on the second plug.

Claims (37)

1. A semiconductor device comprising:

a silicon substrate in which various elements for the semiconductor device are formed;

a first dielectric film formed on the substrate, the first dielectric film having a first contact hole;

a first plug having a low aspect ratio buried in the first contact hole;

a second dielectric film formed on an entire surface of the first dielectric film, the second dielectric film having a second contact hole on the first plug;

a second plug having a low aspect ratio buried in the second contact hole; and

a metal line formed on the second plug,

wherein the second plug has a height less than a height of the first plug such that the second plug has an aspect ratio less than that of the first plug.

2. The device of claim 1 , wherein the first and second plugs are tungsten plugs.

3. The device of claim 1 , wherein the first and second plugs are formed such that an upper width is greater than a lower width and the difference between the upper and lower widths is minimized.

4. The device of claim 1 , wherein the metal line is an aluminum line.

5. The semiconductor device of claim 1 , wherein the second dielectric film has a thickness less than that of the first dielectric film.

6. The semiconductor device of claim 1 , wherein the first and second plugs are provided at the same position as each other.

7. The semiconductor device of claim 1 , further comprising a third dielectric film and a third plug buried in the third dielectric film between the second plug and the metal line.

8. The semiconductor device of claim 7 , wherein the third dielectric film has a thickness less than that of either the first dielectric film or the second dielectric film.

9. The semiconductor device of claim 7 , wherein the third plug has an aspect ratio less than or equal to that of either the first plug or the second plug.

10. The semiconductor device of claim 7 , wherein the first, second, and third plugs are provided at the same position as one another.

11. The semiconductor device of claim 7 , wherein the third plug is a tungsten plug.

12. The semiconductor device of claim 7 , wherein the third plug is formed such that an upper width is greater than a lower width and the difference between the upper and lower widths is minimized.

13. A method for forming a plug structure of a semiconductor device comprising:

forming a silicon substrate;

forming a plurality of device elements for the semiconductor device in the substrate;

forming a first dielectric film on the substrate;

forming a first plug by selectively patterning the first dielectric film to form a first contact hole and burying a conductive material in the first contact hole;

forming a second dielectric film on an entire surface including the first dielectric film;

forming a second plug by selectively patterning the second dielectric film to form a second contact hole on the first plug and burying a conductive material in the second contact hole; and

forming a metal line on the second plug,

wherein the second plug has a height less than a height of the first plug such that the second plug has an aspect ratio less than that of the first plug.

14. The method of claim 13 , wherein the first and second plugs are formed of tungsten.

15. The method of claim 13 , wherein the first and second plugs are formed at the same position as each other.

16. The method of claim 13 , wherein the metal line is formed of aluminum.

17. The method of claim 13 , wherein the second dielectric film is formed to have a thickness less than that of the first dielectric film.

18. The method of claim 13 , further comprising:

between the steps of forming the second plug and forming the metal line, forming a third dielectric film on the entire surface including the second plug, and forming a third plug by selectively patterning the third dielectric film to form a third contact hole on the second plug and burying a conductive material in the third contact hole.

19. The method of claim 18 , wherein the third plug is formed of tungsten.

20. The method of claim 18 , wherein the first, second and third plugs are formed at the same position as one another.

21. The method of claim 18 , wherein the third dielectric film is formed at a thickness less than that of either the first dielectric film or the second dielectric film.

Assignments (9)
CHANGE OF NAME Recorded Nov 19, 2025
From: TESSERA ADVANCED TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.
Reel/Frame 073635/0304 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2015
From: STRATEGIC GLOBAL ADVISORS OF OREGON, INC.
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 035620/0771 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2015
From: DONGBU HITEK CO., LTD.
To: STRATEGIC GLOBAL ADVISORS OF OREGON, INC.
Reel/Frame 035491/0744 →
MERGER Recorded Apr 22, 2015
From: DONGBU ELECTRONICS CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 035469/0801 →
CHANGE OF NAME Recorded Jul 13, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018099/0281 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2005
From: CHUN, IN KYU
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017431/0373 →