Granted Patent B2

US 7,306,989 · App. 11/320,823 · Granted Dec 11, 2007

Abstract

Claims (21)

1. A fabricating method of a semiconductor device, comprising:

forming a first metal layer on a substrate and patterning the first metal layer to form a bottom metal line and a bottom electrode of a capacitor;

forming an interlayer insulating layer on the resulting structure;

forming a via hole in the interlayer insulating layer;

forming a contact by depositing a metal for connecting to the bottom metal line;

after forming the contact, exposing the interlayer insulating layer through planarization using a chemical mechanical polishing (CMP) process;

forming a titanium nitride (TiN) layer on the resulting structure after the CMP process, and forming and patterning a first photoresist layer on the titanium nitride layer;

etching the titanium nitride layer and the interlayer insulating layer to form a trench exposing the bottom electrode;

forming a dielectric layer on the resulting structure, and removing the dielectric layer formed outside the trench; and

forming a second metal layer on the resulting structure to form a top metal line and a top electrode of the capacitor.

2. The fabricating method according to claim 1 , wherein the first metal layer and the second metal layer are formed of aluminum (Al).

3. The fabricating method according to claim 1 , wherein the via hole formed in the interlayer insulating layer exposes the bottom metal line.

4. The fabricating method according to claim 1 , wherein the contact is formed of tungsten (W).

5. The fabricating method according to claim 1 , wherein the dielectric layer is formed of a silicon nitride (SiN) layer.

6. The fabricating method according to claim 5 , wherein the silicon nitride (SiN) layer is formed using a plasma enhanced chemical vapor deposition (PECVD).

7. The fabricating method according to claim 1 , wherein the step of removing of the dielectric layer formed outside the trench comprises:

forming a second photoresist layer patterned on the dielectric layer; and

carrying out an etching process to remove the dielectric layer formed outside the trench.

8. The fabricating method according to claim 7 , wherein a photolithography mask used to form the patterned second photoresist layer is the same as a photolithography mask used to form the first photoresist layer patterned so as to etch the interlayer insulating layer when forming the trench.

9. The fabricating method according to claim 8 , wherein the first photoresist layer and the second photoresist layer are formed of a positive photoresist material and a negative photoresist material, respectively.

10. The fabricating method according to claim 8 , wherein the first photoresist layer and the second photoresist layer are formed of a negative photoresist material and a positive photoresist material, respectively.

Assignments (8)