IP Library Granted Patent US 7,468,300
Granted Patent B2
US 7,468,300 · App. 11/320,859 · Granted Dec 23, 2008

Semiconductor device having high voltage MOS transistor and fabrication method thereof

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Quick Facts
Patent No.
US 7,468,300
App. No.
11/320,859
Granted
Dec 23, 2008
Kind
B2
Abstract

A semiconductor device having a high voltage MOS transistor. The device includes a gate oxide layer disposed between a gate electrode and a substrate on an active area and having relatively thick portions at edges thereof. A fabrication method includes forming on the substrate is a nitride layer having an opening in a high voltage region. An oxide layer is deposited over the substrate and anisotropically etched to remain only on sidewalls of the opening. A first gate oxide layer is formed on the substrate in the opening, and the nitride layer is removed. Then a second gate oxide layer is formed over the substrate such that the second gate oxide layer has a relatively thinner thickness than the first gate oxide layer. Gate electrodes are then formed in the high voltage region and the low voltage region.

Claims (13)

1. A method of fabricating a semiconductor device, the method comprising:

forming a field area in a semiconductor substrate so as to define an active area in a high voltage region and a low voltage region;

forming a nitride layer on the substrate, having an opening in the high voltage region;

depositing an oxide layer over the substrate;

anisotropically etching the oxide layer such that the oxide layer remains only on sidewalls of the opening;

forming a first gate oxide layer on the substrate in the opening;

removing the nitride layer;

forming a second gate oxide layer over the substrate such that the second gate oxide layer has a relatively thinner thickness than the first gate oxide layer;

forming gate electrodes in the high voltage region and the low voltage region; and

forming source/drain around the gate electrodes in the active area of the substrate.

2. The method of claim 1 , wherein the first gate oxide layer has a thickness of 500˜1500 Å and the second gate oxide layer has a thickness of 50˜300 Å.

3. The method of claim 1 , further comprising:

after the forming of the field area, forming a drift area in the substrate of the high voltage region.

Assignments (1)
CHANGE OF NAME Recorded May 23, 2006
From: DONGBU-ANAM SEMICONDUCTOR, INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017663/0468 →