Apparatus and method for adapting a level sensitive device to produce edge-triggered behavior
View Patent ↗A circuit for adapting a level sensitive memory device to exhibit edge-triggered behavior. The adapter circuit can be used with testing modules that expect edge-triggered behavior. The adapting circuit may include address decoding circuitry and output storage and delay circuitry.
1. A device comprising:
a first circuit to detect a mode enable signal; and
a second circuit coupled to the first circuit to hold stable a level sensitive device data output signal from before to after a subsequent leading edge of a clock signal.
2. The device of claim 1 , wherein the level sensitive device data output signal comprises an input signal to the second circuit from one of a random access memory, a memory cache, and a static random access memory.
3. The device of claim 1 , wherein the first circuit includes a selection device to select one of a level sensitive output form of the data output signal and a edge triggered output form of the data output signal.
4. The device of claim 3 , wherein the second circuit includes one of a storage device and a delay device.
5. The device of claim 4 , wherein the second circuit comprises one of a delay flip-flop, a reset-set flip-flop, and a register.
6. The device of claim 4 , further comprising:
a third circuit coupled to the first circuit to convert an encoded address to a fully decoded address.
7. The device of claim 6 , wherein the third circuit comprises one of a write address decode circuit and a read address decode circuit.
8. The device of claim 6 , further comprising:
one of a level sensitive storage device coupled to the second circuit.
9. The device of claim 8 , wherein the storage device is one of random access memory, a memory cache, a latch, and a static random access memory.
10. The device of claim 1 , wherein the clock signal comprises a signal of one of a system clock and a global clock.
11. A method comprising:
receiving a mode enable signal;
holding stable a level sensitive device output over one clock cycle of a clock signal; and
selecting one of a level sensitive output form and an edge triggered output form.
12. The method of claim 11 , wherein holding stable comprises holding stable from a low phase of the clock signal to a subsequent leading edge of the clock signal.
13. The method of claim 11 , wherein holding stable converting the level sensitive device output to an edge triggered output form.
14. The method of claim 11 , wherein holding stable comprises holding a read enable signal high for two clock cycles.
15. The method of claim 11 , wherein the selecting one of a level sensitive output form and edge triggered output form is based on the mode enable signal.
16. The method of claim 15 , further comprising:
converting an encoded address to a fully decoded address.
17. A device comprising:
a means for converting a level sensitive device output to an edge triggered output format; and
a means for selecting one of a level sensitive output format and an edge triggered output format based on a mode enable signal.
18. The device of claim 17 , further comprising:
a means for converting an encoded address to a fully decoded address.