Method of forming metal line in semiconductor device
A method of forming a metal line in a semiconductor device reduces production costs through a simplified fabricating process. The method includes steps of forming a first metal line on a semiconductor substrate; forming an insulating layer over the semiconductor substrate including the first metal line; coating a photoresist on the insulating layer; aligning a diffraction mask having regions or patterns differing from each other in transmittance over the photoresist; patterning the photoresist by exposure and development using the diffraction mask to form a patterned photoresist having regions that differ in thickness; forming a via hole and a trench by etching the patterned photoresist and the insulating layer simultaneously to expose a prescribed portion of the first metal line; removing the remaining photoresist; and forming a second metal line and a contact in the trench and the via hole.
1 . A method of fabricating a semiconductor device, comprising:
patterning a photoresist on an insulating layer over a semiconductor substrate including a first metal line by exposure and development using a diffraction mask having regions of different transmittance to form a patterned photoresist having regions that differ in thickness;
forming a via hole and a trench by etching the patterned photoresist and the insulating layer simultaneously to expose a portion of a surface of the first metal line;
removing the remaining photoresist; and
forming a second metal line and a contact in the trench and the via hole.
2 . The method of claim 1 , further comprising the step of forming a barrier metal layer in the via hole and the trench.
3 . The method of claim 1 , wherein the insulating layer comprises a low-k material.
4 . The method of claim 3 , wherein the low-k material comprises fluorine-doped silicate glass, undoped silicate glass and/or an oxide of phosphorus-doped silicon tetrahydride (P—SiH 4 ).
5 . The method of claim 1 , wherein the insulating layer has a thickness at least twice that of the second metal line.
6 . The method of claim 1 , wherein the diffraction mask comprises a shielding region adapted to shield light, a transmitting region or aperture adapted to transmit light, and a slit region having a reduced transmittance, adapted to transmit part of the light.
7 . The method of claim 1 , wherein a thickness of the photoresist remaining in a trench-defining area is equal to or greater than (t 1 −t 2 )/s, where t 2 is a thickness of the second metal line, t 1 is a thickness of the insulating layer, and s is an etch selection ratio of the insulating layer relative to the photoresist.
8 . The method of claim 1 , further comprising aligning the diffraction mask over the photoresist.
9 . The method of claim 1 , further comprising coating the photoresist on the insulating layer.
10 . The method of claim 9 , further comprising forming the insulating layer over the semiconductor substrate including the first metal line.
11 . The method of claim 10 , further comprising forming the first metal line on the semiconductor substrate.
12 . The method of claim 1 , wherein the second metal line comprises copper.
13 . The method of claim 12 , further comprising the step of forming a barrier metal layer comprising TiN, Ta, TaN, WN x , or TiAl(N) in the via hole and the trench.
14 . The method of claim 12 , wherein forming the copper film comprises electroplating.
15 . The method of claim 13 , further comprising the step of forming a copper seed layer on the barrier metal layer.
16 . The method of claim 12 , wherein forming the copper seed layer comprises PVD, sputtering, or CVD.
17 . The method of claim 1 , wherein the exposed portion of the first metal line corresponds to the via hole in the insulating layer and the contact.
18 . The method of claim 1 , wherein a line-defining region of the diffraction mask has a transmittance of from 20% to 80% of a transmittance in a via hole-defining region of the diffraction mask.