Method for forming metal line of semiconductor device
View Patent ↗A method for forming a metal line of a semiconductor device uses a low dielectric constant material as an interlayer dielectric layer and treats a surface of the interlayer dielectric layer with plasma to prevent moisture and ammonia from being adsorbed in the low dielectric constant material. The method for forming a metal line of a semiconductor device includes forming a lower metal line layer on a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on an entire surface including the lower metal line layer, forming a plasma layer by treating a surface of the interlayer dielectric layer with plasma, forming a photoresist pattern on the plasma layer, forming a via hole using the photoresist pattern as a mask to open the lower metal line layer, and forming a via contact by burying a metal material in the via hole.
1. A method for forming a semiconductor device, the method comprising:
forming a lower metal line layer on top of and in direct contact with a semiconductor substrate;
forming an etch stop layer of at least one of SiN, SiC, SiCN, and SiCO, on top of and in direct contact with the lower metal line layer;
forming an interlayer dielectric layer on top of and in direct contact with the etch stop layer;
forming a plasma layer on top of and in direct contact with the interlayer dielectric layer by treating the surface of the interlayer dielectric layer with plasma at a temperature of 30° C. to 400° C., wherein forming the plasma layer comprises treating the surface of the interlayer dielectric layer with plasma using O 2 gas;
forming a photoresist pattern on top of and in direct contact with the plasma layer;
removing the plasma layer and the interlayer dielectric layer using the photoresist pattern as a mask to form a via hole exposing the etch stop layer;
removing the etch stop layer externally exposing the lower metal line layer;
forming a metal material on the plasma layer and in the via hole;
forming a first antidiffusion layer on the metal material;
removing the first antidiffusion layer, the metal material, and the plasma layer by a CMP process until the interlayer dielectric layer is exposed to form a via contact in the via hole; and
forming a second antidiffusion layer over the interlayer dielectric layer and via contact following the CMP process.
2. The method as claimed in claim 1 , wherein forming the plasma layer further comprises treating the surface of the interlayer dielectric layer with plasma using He, H 2 , Ar, Co, or N 2 in addition to O 2 .
3. The method as claimed in claim 1 , wherein forming a plasma layer comprises forming a SiO 2 layer.
4. The method as claimed in claim 1 , wherein forming the plasma layer comprises treating the surface of the interlayer dielectric layer with plasma at a power of about 1 W to 10 KW.
5. The method as claimed in claim 1 , wherein forming the plasma layer comprises treating the surface of the interlayer dielectric layer with plasma at a pressure of about 0.1 torr to 10 torr.
6. The method as claimed in claim 1 , wherein forming the lower metal line layer comprises forming a lower line layer of Cu.
7. The method as claimed in claim 1 , wherein forming the interlayer dielectric layer comprises forming a layer of low-k dielectric material.
8. The method as claimed in claim 1 , wherein forming the interlayer dielectric layer comprises forming a layer of low-k dielectric material having a dielectric constant value of 3 or less.
9. The method as claimed in claim 1 , further comprising planarizing the metal material using a CMP process after burying the metal material in the via hole.
10. The method as claimed in claim 1 , wherein forming the first antidiffusion layer comprises forming a layer comprising at least one of Ta, TaN, W, WN, Ti, TiN, or a composite thereof.
11. A method for forming a semiconductor device, the method comprising:
forming a lower metal line layer on top of and in direct contact with a semiconductor substrate;
forming an etch stop layer of at least one of SiN, SiC, SiON, and SiCO, on top of and in direct contact with the lower metal line layer;
forming an interlayer dielectric layer on top of and in direct contact with the etch stop layer;
forming a plasma layer on top of and in direct contact with the interlayer dielectric layer by treating the surface of the interlayer dielectric layer with plasma at a temperature of 30° C. to 400° C., wherein forming the plasma layer comprises treating the surface of the interlayer dielectric layer with plasma using NH 3 gas;
forming a photoresist pattern on top of and in direct contact with the plasma layer;
removing the plasma layer and the interlayer dielectric layer using the photoresist pattern as a mask to form a via hole exposing the etch stop layer;
removing the etch stop layer externally exposing the lower metal line layer;
forming a metal material on the plasma layer and in the via hole;
forming a first antidiffusion layer on the metal material;
removing the first antidiffusion layer, the metal material, and the plasma layer by a CMP process until the interlayer dielectric layer is exposed to form a via contact in the via hole; and
forming a second antidiffusion layer over the interlayer dielectric layer and via contact following the CMP process.
12. The method as claimed in claim 11 , wherein forming the plasma layer further comprises treating the surface of the interlayer dielectric layer with plasma using He, H 2 , Ar, Co, or N 2 in addition to NH 3 .
13. The method as claimed in claim 11 , wherein forming the plasma layer comprises forming a layer of at least one of SiN, SiON, SiCO or SiON.