Cylinder-type capacitor and storage device, and method(s) for fabricating the same
View Patent ↗A one cylinder storage device and a method for fabricating a capacitor are disclosed, realizing simplified fabrication by overexposure with a mask having a plurality of holes, in which the method includes forming a contact hole in an insulating layer on a semiconductor substrate; forming a conductive layer on the insulating layer to fill the contact hole; forming a photoresist layer on the conductive layer; forming a photoresist layer pattern by overexposure and generating a side lobe phenomenon; forming a cylindrical lower electrode by patterning the conductive layer using the photoresist layer pattern as a mask; and forming a dielectric layer and an upper electrode covering the lower electrode.
1. A method for fabricating a cylinder-type storage device, the method comprising:
forming a first conductive layer above a semiconductor substrate;
forming a photoresist layer upon the first conductive layer;
overexposing the photoresist layer to radiation passed through a phase shift mask, having partially transmissive areas and transparent areas, to create a virtual image on the semiconductor substrate from a peak and to produce a pattern in the photoresist layer having at least one substantially cylindrically-shaped structure corresponding to a boundary between the partially transmissive areas and the transparent areas; and
etching portions of the conductive layer not covered by the cylindrically-shaped structure to form a lower electrode of the cylinder-type storage device.
2. The method as recited in claim 1 , wherein the step of etching portions of the first conductive layer produces a lower electrode with sidewalls, which are substantially cylindrical in shape and substantially constant in thickness along a vertical length of the lower electrode.
3. The method as recited in claim 1 , wherein after the step of etching, the method further comprises:
removing remaining portions of the photoresist layer;
forming a second dielectric layer upon the lower electrode formed from the first conductive layer; and
forming a second conductive layer upon the second dielectric layer to form an upper electrode of the cylinder-type storage device.
4. The method as recited in claim 3 , wherein the second dielectric layer is selected from the group consisting of boron phosphorus silicate glass (BPSG), undoped silicate glass (USG), spin-on-glass (SOG), tetracthylorthosilicate glass (TEOS), aluminum oxide (Al 2 O 3 ), tantalum pentoxide (Ta 2 O 5 ), barium titanate (BaTiO 3 ), titanium oxide (TiO 2 ), and an oxide of one or more of the following: silicon (Si), nitrogen (N), aluminum (Al), tantalum (Ta), barium (Ba), strontium (Sr), titanium (Ti), and lead (Pb).
5. The method as recited in claim 3 , wherein the second conductive layer is selected from the group consisting of doped or undoped polysilicon, aluminum, cobalt, cobalt silicide, copper, iron, nickel, nickel-iron-chromium, platinum, tantalum, tantalum nitride, titanium, titanium nitride, titanium silicide, tungsten, tungsten silicide, and molybdenum silicide.
6. The method as recited in claim 1 , wherein prior to forming the first conductive layer, the method comprises:
forming a first dielectric layer above the semiconductor substrate; and
forming an etch stop layer upon portions of the first dielectric layer, such that the first conductive layer is subsequently formed upon the etch stop layer and the first dielectric layer.
7. The method as recited in claim 6 , wherein the steps of forming the first dielectric layer and the etch stop layer further comprise:
etching the first dielectric layer to form a first opening within the first dielectric layer for exposing an underlying conductive structure; and
etching the etch stop layer to form a second opening within the etch stop layer, wherein opposing sidewalls of the second opening are laterally spaced from opposing sidewall surfaces of the first opening.
8. The method as recited in claim 7 , wherein the step of forming the first conductive layer comprises depositing a conductive material within the first and second openings to form a conductive plug for contacting the underlying conductive structure.
9. The method as recited in claim 8 , wherein the conductive material comprises polysilicon.
10. The method as recited in claim 6 , wherein the first dielectric layer is selected from the group consisting of silicon dioxide (SiO 2 ), tetracthylorthosilicate (TEOS)-based silicon dioxide, silicon nitride (Si x N y ), silicon dioxide/silicon nitride/silicon dioxide (ONO), silicon carbide, silicon-rich oxide (SRO), a SiOC-based insulator, carbonated polymers, fluorine-doped silicon dioxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and fluorosilicate glass (FSG).
11. The method as recited in claim 6 , wherein the etch stop layer comprises silicon nitride.
12. The method as recited in claim 1 , wherein the phase shift mask includes a hole-shaped or donut-shaped pattern therein.
13. The method as recited in claim 1 , wherein the partially transmissive areas of the phase shift mask have a transmittance of 6% to 15%.
14. The method as recited in claim 1 , wherein the transparent areas of the phase shift mask have a transmittance of 100%.
15. The method as recited in claim 1 , wherein overexposing is performed at and energy level from about one and a half times to about two and a half times that of a normal exposure.
16. The method as recited in claim 1 , wherein overexposing enables removal of at least a portion of the photoresist layer corresponding to the partially transmissive areas.
17. The method as recited in claim 1 , wherein the phase shift mask comprises a plurality of high transmittance portions in a matrix of rows and columns.
18. The method as recited in claim 1 , wherein the semiconductor substrate comprises a wafer.
19. The method as recited in claim 1 , further comprising removing a portion of the photoresist layer corresponding to the partially transmissive areas.
20. The method as recited in claim 19 , wherein removing the portion of the photoresist comprises developing said exposed photoresist.
21. The method as recited in claim 1 , wherein the first conductive layer is selected from the group consisting of doped or undoped polysilicon, aluminum, cobalt, cobalt silicide, copper, iron, nickel, nickel-iron-chromium, platinum, tantalum, tantalum nitride, titanium, titanium nitride, titanium silicide, tungsten, tungsten silicide, and molybdenum silicide.