Antifuse having uniform dielectric thickness and method for fabricating the same

1. A method for fabricating an antifuse, said method comprising steps of:

forming a contact and/or via hole in an insulating layer on an underlying conductive layer;

forming a lower metal layer that contacts inner surfaces of the contact and/or via hole and a top surface of the insulating layer and that partially fills said contact and/or via hole;

forming a filling layer on the lower metal layer, wherein the filling layer partially fills the contact and/or via hole such that a recess having a predetermined depth is formed in said contact and/or via hole;

forming an antifuse material layer that contacts an upper surface of the filling layer and an inner surface of the lower metal layer in said contact and/or via hole, wherein the antifuse material layer contacts the lower metal layer at both an external region and an internal region of said contact and/or via hole; and

forming an upper metal layer on the antifuse material layer.

2. The method of claim 1 , wherein forming the antifuse material layer at least partially fills said recess in the contact and/or via hole.

3. The method of claim 1 , wherein the step of forming the filling layer includes the steps of:

depositing a tungsten layer sufficiently to fill the contact and/or via hole and cover the lower metal layer;

planarizing the tungsten layer to remove tungsten from areas other than the contact and/or via hole; and

etching the remaining tungsten layer to form said recess in the contact and/or via hole.

4. The method of claim 3 , wherein etching the tungsten layer comprises wet etching with an etchant and/or cleaner comprising H 2 O 2 .

5. The method of claim 3 , wherein forming said antifuse material layer comprises covering an upper surface of said filling layer, a side surface of said recess, and a top surface of said insulating layer.

6. The method of claim 5 , wherein forming the antifuse material layer at least partially fills said recess in the contact and/or via hole.

7. The method of claim 1 , wherein the antifuse material layer comprises amorphous silicon.

8. The method of claim 7 , wherein forming the antifuse material layer comprises depositing the amorphous silicon by chemical vapor deposition.

9. The method of claim 1 , wherein each of the lower and upper metal layers comprise titanium.

10. The method of claim 1 , wherein the lower metal layer provides a diffusion barrier function.

11. The method of claim 10 , wherein the upper metal layer provides a diffusion barrier function.

12. The method of claim 1 , wherein the upper metal layer provides a diffusion barrier function.

13. The method of claim 1 , wherein each of the lower and upper metal layers comprise an adhesive metal layer and a baffler layer.

14. The method of claim 13 , wherein said adhesive metal layer comprises titanium.

15. The method of claim 13 , wherein said baffler layer comprises titanium nitride.

16. The method of claim 1 , further comprising depositing an overlying layer on said upper metal layer.

17. The method of claim 16 , further comprising programming the antifuse, thereby electrically interconnecting said overlying layer to said underlying conductive layer.

18. The method of claim 16 , wherein said overlying layer comprises one or more materials selected from the group consisting of aluminum, copper, polysilicon and metal silicides.

19. The method of claim 1 , further comprising forming the insulating layer on the underlying conductive layer.

20. The method of claim 19 , wherein the insulating layer comprises one or more materials selected from the group consisting of silicon rich oxide (SRO), silicon dioxide, undoped silicon glass (USG), silane-based oxide, TEOS-based oxide, oxide-nitride-oxide (ONO), borophosphosilicate glass (BPSG), and phosphosilicate glass (PSG).