CMOS image sensor and method for fabricating the same
View Patent ↗Provided are a CMOS image sensor in which microlenses are formed in a remaining space in a patterned light shielding layer to improve image sensor characteristics and to protect the microlenses during packaging, and a method of fabricating the same. The CMOS image sensor may include: a semiconductor substrate; at least one photodiode on or in the semiconductor substrate; a first insulating layer on the substrate including the photodiode(s); a plurality of metal lines on and/or in the first insulating layer; a second insulating layer on the first insulating layer including at least some of the metal lines; a patterned light shielding layer on the second insulating layer; and microlenses in a remaining space on the second insulating layer.
1. A method of fabricating a CMOS image sensor comprising:
forming a patterned light shielding layer comprising a plurality of light shielding structures on a planarized insulating layer, the planarized insulating layer on an underlying insulating layer having a plurality of metal lines thereon and/or therein, the underlying insulating layer on a semiconductor substrate including a plurality of photodiodes;
forming a microlens material on the planarized insulating layer and the patterned light shielding layer;
planarizing the microlens material by polishing, such that the planarized microlens material has a thickness substantially equal to that of the light shielding layer; and
baking the planarized microlens material to form microlenses on the planarized insulating layer between the light shielding structures.
2. the method according to claim 1 , wherein the patterned light shielding layer and the microlenses do not overlap each other.
3. The method according to claim 1 , further comprising the step of:
selectively etching the planarized microlens material before the step of baking the planarized microlens material.
4. The method according to claim 3 , wherein a peripheral portion of the planarized microlens material is selectively etched.
5. The method according to claim 3 , wherein the light shielding layer comprises at least one of carbon, graphite, or CrO 3 .
6. The method according to claim 3 , wherein the planarized insulating layer comprises an oxide layer.
7. The method according to claim 3 , wherein the planarized insulating layer comprises a nitride layer.
8. The method according to claim 3 , wherein planarizing the planarized insulating layer comprises chemical mechanical polishing (CMP).
9. The method according to claim 3 , wherein polishing comprises chemical mechanical polishing (CMP).
10. The method according to claim 1 , wherein the light shielding layer comprises at least one of carbon, graphite, or CrO 3 .
11. The method according to claim 1 , wherein the planarized insulating layer comprises an oxide layer.
12. The method according to claim 1 , wherein the planarized insulating layer comprises a nitride layer.
13. The method according to claim 1 , wherein planarizing the planarized insulating layer comprises chemical mechanical polishing (CMP).
14. The method according to claim 1 , wherein polishing comprises chemical mechanical polishing (CMP).