Reverse MOS (RMOS) transistor, and methods of making and using the same
A metal-oxide-semiconductor transistor having a reverse current control mechanism (RMOS transistor) is described. The RMOS transistor generally includes a semiconductor substrate, a gate electrode on an oxide layer on the substrate, source and drain electrodes at opposite sides of the gate electrode, and a carrier region having a carrier with a type opposite to that of the substrate, in the substrate below the gate, source and drain electrodes. The carrier region maintains a turn-on state where current can flow between drain and source regions without a bias voltage applied to the gate electrode. When a bias voltage is applied to the gate electrode, the carrier region is electrically disconnected to turn off the transistor.
1 . A transistor comprising:
a semiconductor substrate;
an oxide layer on the substrate;
a gate on the oxide layer;
source and drain electrodes at opposite sides of the gate; and
a carrier region doped with a carrier having a type opposite to that of the substrate, in the substrate below the gate and the source and drain electrodes;
said carrier region allowing current to flow between the drain and source electrodes when no bias voltage is applied to the gate (and/or a corresponding gate electrode), and disabling current from flowing when a bias voltage is applied to the gate (and/or the corresponding gate electrode).
2 . The transistor of claim 1 , wherein the carrier region has a shallow portion below the gate electrode, the shallow portion having a depth smaller than other portions of the carrier region.
3 . The transistor of claim 1 , wherein the semiconductor substrate comprises a single crystal silicon wafer.
4 . The transistor of claim 3 , wherein the semiconductor substrate comprises a P-doped single crystal silicon wafer having an N-well therein.
5 . The transistor of claim 4 , wherein the carrier region comprises a P-type dopant, and the transistor further comprises P-type source and drain terminals in the N-well, below the source and drain electrodes.
6 . The transistor of claim 5 , wherein the carrier region under the gate material comprises a relatively shallow ion implant, and the source and drain terminals each comprise a relatively deep ion implant.
7 . The transistor of claim 3 , wherein the semiconductor substrate comprises an N-doped single crystal silicon wafer having a P-well therein.
8 . The transistor of claim 7 , wherein the carrier region comprises an N-type dopant, and the transistor further comprises N-type source and drain terminals in the P-well, below the source and drain electrodes.
9 . The transistor of claim 8 , wherein the carrier region under the gate material comprises a relatively shallow ion implant, and the source and drain terminals each comprise a relatively deep ion implant.
10 . The transistor of claim 1 , wherein the semiconductor substrate further comprises source and drain regions doped with a carrier having a type opposite to that of the substrate, in the substrate below the source and drain electrodes.
11 . A method of making a transistor, comprising:
doping at least a channel region in an active area of a semiconductor substrate with a carrier having a type opposite to that of the active area;
forming an oxide layer on the substrate;
forming a gate on the oxide layer; and
forming a gate electrode on the gate and source and drain electrodes at opposite sides of the gate.
12 . The method of claim 11 , wherein the carrier region is doped sufficiently to allow current to flow between the drain and source terminals when no bias voltage is applied to the gate, and to disable current from flowing when a bias voltage is applied to the gate electrode.
13 . The method of claim 11 , further comprising forming a well in the substrate, prior to doping the channel region.
14 . The method of claim 11 , further comprising forming an isolation structure on and/or in the substrate to define the active area.
15 . The method of claim 11 , further comprising forming source and drain terminals in the substrate below the source and drain electrodes, the source and drain terminals having a same carrier type as that of the channel region.
16 . The method of claim 15 , wherein doping at least the channel region comprises implanting ions into the active area at a relatively low energy, and forming the source and drain terminals comprises implanting ions into in source and drain regions of the substrate at a relatively high energy.
17 . A method of operating a MOS transistor, comprising:
applying a bias voltage to a gate and/or gate electrode of the transistor to turn off the transistor or reduce its transconductance, the transistor comprising an oxide layer on a semiconductor substrate, the gate on the oxide layer, source and drain electrodes at opposite sides of the gate, and a carrier region doped with a carrier having a type opposite to that of the substrate, the carrier region in the substrate below the gate and the source and drain electrodes; and
not applying the bias voltage to a gate and/or gate electrode of the transistor to disable current from flowing between the drain and source electrodes.