Data line driver including a plurality of cascaded data line driver sections having long sampling period of video signals

1 . A data line driver for driving N (N=2, 3, . . . ) data lines of a display apparatus including cascaded M (M=2, 3, . . . ) data line driver sections, each of said data line driver sections comprising:

a digital signal receiving and holding section adapted to receive and hold N/M digital video signals in synchronization with a first clock signal;

a digital/analog converter adapted to perform a digital/analog conversion upon said N/M digital video signals in synchronization with a second clock signal whose rate is smaller than that of said first clock signal, to generate N/M analog video signals; and

an analog video signal receiving and holding section adapted to receive and hold said N/M analog video signals.

2 . The data line driver as set forth in claim 1 , wherein said digital signal receiving and holding section comprises:

a first transfer circuit adapted to shift a first start signal in synchronization with said first clock signal to generate a first latch signal;

a first digital signal storing circuit adapted to latch said digital video signals in synchronization with said first latch signal;

a second digital signal storing circuit adapted to latch all said digital video signals in said first digital signal storing circuit in synchronization with a strobe signal; and

a third digital signal storing circuit adapted to sequentially latch respective parts of said digital video signals latched in said second digital signal storing circuit in synchronization with said second clock signal.

3 . The data line driver as set forth in claim 2 , wherein said digital signal receiving and holding section further comprises a second transfer circuit adapted to shift a second start signal in synchronization with said second clock signal to generate a second latch signal, so that said parts of said digital video signals are sequentially transferred from said second digital signal storing circuit to said third digital signal storing circuit in synchronization with said second latch signal.

4 . The data line driver as set forth in claim 1 , wherein said analog signal receiving and holding section comprises:

a sample/hold circuit adapted to sample and hold said analog video signals of said digital/analog converter in synchronization with said second clock signal; and

an output buffer adapted to output said analog video signals of said sample/hold circuit in synchronization with an output enable signal.

5 . The data line driver as set forth in claim 4 , wherein said analog signal receiving and holding section further comprises a third transfer circuit adapted to shift a third start signal in synchronization with said second clock signal to generate a third latch signal, so that said sample/hold circuit samples said analog video signals of said digital/analog converter in synchronization with said third latch signal.

6 . The data line driver as set forth in claim 1 , wherein each of said data line driver sections further comprises an amplifier circuit adapted to amplify said analog video signals.

7 . A data line driver for driving N (N=2, 3, . . . ) data lines of a display apparatus including cascaded M (M=2, 3, . . . ) data line driver sections, each of said data line driver sections further including cascaded L (L=2, 3, . . . ) sub data line drivers, each of said sub data line driver sections comprising:

a digital signal receiving and holding section adapted to receive and hold N/(M*L) digital video signals in synchronization with a first clock signal;

a digital/analog converter adapted to perform a digital/analog conversion upon said N/(M* L) digital video signals in synchronization with a second clock signal whose rate is smaller than that of said first clock signal, to generate N/(M*L) analog video signals; and

an analog video signal receiving and holding section adapted to receive and hold said N/(M* L) analog video signals.

8 . The data line driver as set forth in claim 7 , wherein said digital signal receiving and holding section comprises:

a first transfer circuit adapted to shift a first start signal in synchronization with said first clock signal to generate a first latch signal;

a first digital signal storing circuit adapted to latch said digital video signals in synchronization with said first latch signal;

a second digital signal storing circuit adapted to latch all said digital video signals in said first digital signal storing circuit in synchronization with a strobe signal; and

a third digital signal storing circuit adapted to sequentially latch respective parts of said digital video signals latched in said second digital signal storing circuit in synchronization with said second clock signal.

9 . The data line driver as set forth in claim 8 , wherein said digital signal receiving and holding section further comprises a second transfer circuit adapted to shift a second start signal in synchronization with said second clock signal to generate a second latch signal, so that said parts of said digital video signals are sequentially transferred from said second digital signal storing circuit to said third digital signal storing circuit in synchronization with said second latch signal.

10 . The data line driver as set forth in claim 7 , wherein said analog signal receiving and holding section comprises:

a sample/hold circuit adapted to sample and hold said analog video signals of said digital/analog converter in synchronization with said second clock signal; and

an output buffer adapted to output said analog video signals of said sample/hold circuit in synchronization with an output enable signal.

11 . The data line driver as set forth in claim 10 , wherein said analog signal receiving and holding section further comprises a third transfer circuit adapted to shift a third start signal in synchronization with said second clock signal to generate a third latch signal, so that said sample/hold circuit samples said analog video signals of said digital/analog converter in synchronization with said third latch signal.

12 . The data line driver as set forth in claim 7 , wherein each of said data line driver sections further comprises an amplifier circuit adapted to amplify said analog video signals.

13 . A method for driving a data line driver for driving N (N=2, 3, . . . ) data lines of a display apparatus including cascaded M (M=2, 3, . . . ) data line driver sections, comprising:

receiving and holding N/M digital video signals by each of said data line driver sections in synchronization with a first clock signal;

performing a digital/analog conversion upon said N/M digital video signals by each of said data line driver sections in synchronization with a second clock signal whose rate is smaller than that of said first clock signal, to generate N/M analog video signals; and

receiving and holding said N/M analog video signals by each of said data line driver sections.

14 . A method for driving a data line driver for driving N (N=2, 3, . . . ) data lines of a display apparatus including cascaded M (M=2, 3, . . . ) data line driver sections, each of said data line driver sections further including cascaded L (L=2, 3, . . . ) sub data line drivers comprising:

receiving and holding N/M digital video signals by each of said sub data line driver sections in synchronization with a first clock signal;

performing a digital/analog conversion upon said N/M digital video signals by each of said sub data line driver sections in synchronization with a second clock signal whose rate is smaller than that of said first clock signal, to generate N/M analog video signals; and

receiving and holding said N/M analog video signals by each of said sub data line driver sections.