Method and circuit for the detection of solder-joint failures in a digital electronic package

1. A method of testing the integrity of a solder-joint network for a digital electronic package, comprising:

applying power to the digital electronic package;

applying a time-varying voltage to a first end of and through a first solder-joint network including at least one solder-joint connection and at least one in-series powered-on I/O buffer on a die in the electronic package to charge a charge-storage component at a second end of the first solder-joint network; and

measuring a voltage caused by the charging of the charge-storage component as a measure of the resistance of the first solder-joint network.

2. The method of claim 1 , wherein said first solder-joint network includes at least one said solder-joint connection between the package and a printed wire board.

3. The method of claim 1 , wherein said first solder-joint network includes at least one said solder-joint connection between the die and the package.

4. The method of claim 1 , where said first solder-joint network includes at least one said solder-joint connection between the die and said I/O buffer.

5. The method of claim 1 , wherein said at least one solder-joint connection comprises a solder ball joint.

6. The method of claim 1 , wherein the charge-storage component comprises a capacitor.

7. The method of claim 1 , wherein the time-varying voltage is applied as a binary pulse and measured as a binary voltage.

8. The method of claim 1 , wherein application of the time-varying voltage is initiated upon application of power to the digital electronic package.

9. The method of claim 1 , wherein a plurality of said first solder-joint networks are positioned near the corners of the digital electronic package.

10. The method of claim 1 , wherein said at least one I/O buffer includes an output buffer, and wherein the time-varying voltage is applied by write logic on the die to and through the output buffer to said at least one solder-joint connection to charge the charge-storage device and the voltage caused by the charging of the charge-storage component is measured by read logic on the die through a second solder-joint network including a second solder-joint connection and an input buffer as a measure of the resistance of the first solder-joint network.

11. The method of claim 1 , wherein said at least one I/O buffer includes an input buffer and an output buffer, and wherein the time-varying voltage is applied by write logic outside the package to and through a first solder-joint connection, in the input buffer, out the output buffer and through a second solder-joint connection to charge the charge-storage device and the voltage caused by the charging of the charge-storage component is measured by read logic outside the package as a measure of the resistance of the first solder-joint network.

12. The method of claim 1 , wherein the digital electronic package is an FPGA or a microcontroller in a Ball Grid Array package.

13. A method of testing the integrity of a first solder-joint network including at least one solder-joint connection and at least one in-series I/O buffer on a die in a digital electronic package, comprising:

applying power to the digital electronic package;

using write logic on the die to apply a time-varying voltage to and through the powered-on output buffer and through said at least one solder-joint connection to charge a charge-storage component; and

using read logic on the die to measure a voltage caused by the charging of the charge-storage component through a second solder-joint network including a second solder-joint connection and an input buffer as a measure of the resistance of the first solder-joint network.

14. The method of claim 13 , wherein said first solder-joint network includes at least one said solder-joint connection between said output buffer and said die and at least one said solder-joint connection between the die and the package.

15. The method of claim 14 , wherein said first solder-joint network further includes at least one said solder-joint connection between said package and a printed wire board.

16. The method of claim 13 , wherein the write logic applies the time-varying voltage as a binary pulse and the read logic measures the voltage as a binary voltage.

17. A method of providing testing the integrity of solder-joint networks, characterized by:

providing a digital electronic package configured to form an array of external solder-joints and a die mounted therein, said die including an array of operational buffer circuits connected through I/O contacts to respective external solder-joints that form said operational solder-joint networks, an operational buffer circuit being designated as a monitored circuit in which the monitored solder-joint network includes at least one external solder joint connection and at least one in-series I/O buffer on the die;

applying power to the digital electronic package;

terminating the monitored solder-joint network with a charge-storage component;

applying a time-varying voltage to and through the monitored solder-joint network to charge the charge-storage component; and

measuring a voltage caused by the charge stored on the charge-storage component as a measure of the resistance of the monitor solder-joint network and an indicator of the integrity of the operational solder-joint networks.