IP Library Granted Patent US 7,508,058
Granted Patent B2
US 7,508,058 · App. 11/330,307 · Granted Mar 24, 2009

Stacked integrated circuit module

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,508,058
App. No.
11/330,307
Granted
Mar 24, 2009
Kind
B2
Abstract

The present invention provides an improvement on the use of flexible circuit connectors for electrically coupling IC devices to one another in a stacked configuration by use of the flexible circuit to provide the connection of the stacked IC module to other circuits. Use of the flexible circuit as the connection of the IC module allows the flexible circuit to provide strain relief and allows stacked IC modules to be assembled with a lower profile than with previous methods. The IC module can be connected to external circuits through the flexible circuit connectors by a variety of means, including solder pads, edge connector pads, and socket connectors. This allows for IC devices to occupy less space then with previous methods, which is beneficial in modules such as memory modules with multiple, stacked memory devices.

Claims (18)

1. A circuit module comprising:

a flexible circuit having first and second sides each of which sides exhibits first and second pluralities of connective sites, the first and second pluralities of connective sites being adapted for connection to leads of leaded packaged ICs;

first and second leaded packaged ICs, each one of which has an upper and a lower major surface and plural peripheral sides, a first plurality of leads emergent from a first one of the plural peripheral sides of each of the respective leaded packaged ICs, the first plurality of leads of the first leaded packaged IC being directly connected to the first plurality of connective sites of the first side of the flex circuit while the lower surface of the first leaded packaged IC is immediately adjacent to and in contact with the first side of the flex circuit and the first plurality of leads of the second leaded packaged IC being directly connected to the first plurality of connective sites of the second side of the flex circuit while the lower surface of the second leaded packaged IC is immediately adjacent to and in contact with the second side of the flex circuit.

2. The circuit module of claim 1 further comprising a second plurality of leads emergent from a second one of the plural peripheral sides of each of the respective first and second leaded packaged ICs and the second plurality of leads of the first leaded packaged IC being connected to the second plurality of connective sites of the first side of the flex circuit and the second plurality of leads of the second leaded packaged IC being connected to the second plurality of connective sites of the second side of the flex circuit.

3. The circuit module of claims 1 or 2 in which the flex circuit emerges from between the first and second leaded packaged ICs and exhibits a third plurality of connective sites for connection of the circuit module to an application environment.

4. The circuit module of claim 3 in which the third plurality of connective sites is adapted for connection to a printed circuit board.

5. The circuit module of claim 3 in which the third plurality of connective sites is adapted for connection to a socket connector.

6. The circuit module of claims 1 , 2 , 3 , 4 or 5 in which the first and second leaded packaged ICs are flash memory devices.

7. The circuit module of claim 1 in which the leads of each of the first and second leaded packaged ICs are reconfigured before connection to the flex circuit so as to confine the lead in a space defined by firstand second planes defined by the upper and lower major surfaces of the first and second leaded packaged ICs respectively.

8. A circuit module comprising:

first and second leaded packaged ICs, each of which has an upper major surface defining a plane PU and a lower major surface defining a plane PL and plural peripheral sides, a first one of said plural peripheral sides having an emergent first plurality of leads and a second one of said plural peripheral sides having an emergent second plurality of leads, the first plurality of leads having been configured to be within the space defined by PL and PU;

a flex circuit disposed between the first and second packaged ICs and emergent in part from between the first and second packaged ICs, the flex circuit having first and second pluralities of connective sites along each of first and second major flex surfaces and a third plurality of connective sites along the flex circuit, the first leaded packaged IC being directly connected to the first and second connective sites along the first major flex surface through the first and second pluralities of leads, respectively, of the first leaded packaged IC and there being contact between the lower major surface of the first leaded packaged IC and the first major flex surface of the flex circuit and the second leaded packaged IC being directly connected to the first and second connective sites along the second major flex surface through the first and second pluralities of leads, respectively, of the second leaded packaged IC and there being contact between the lower major surface of the second leaded packaged IC and the second major flex surface of the flex circuit.

9. The circuit module of claim 8 in which an adhesive is disposed between the lower major surface of the first leaded packaged IC and the first major surface of the flex circuit.

10. The circuit module of claim 8 in which an adhesive is disposed between the lower major surface of the second leaded packaged IC and the secondmajor surface of the flex circuit.

11. The circuit module of claims 8 , 9 , or 10 in which the first and second leaded packaged ICs are flash memory circuits.

12. The circuit module of claim 8 in which the first and second pluralities of connective sites are oriented in a first direction and the third-plurality of connective sites are oriented in a second direction different from the first direction.

13. The circuit module of claim 8 in which the third plurality of connective sites is configured for connection to an edge connector.

14. The circuit module of claim 8 in which the third plurality of connective sites are configured as a socket connector.

Assignments (5)
MERGER Recorded Dec 27, 2015
From: OVID DATA CO. LLC
To: TAMIRAS PER PTE. LTD., LLC
Reel/Frame 037373/0481 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2012
From: ENTORIAN TECHNOLOGIES INC.
To: OVID DATA CO. LLC
Reel/Frame 029389/0672 →
MERGER Recorded Oct 25, 2012
From: ENTORIAN TECHNOLOGIES L.P.
To: ENTORIAN GP LLC
Reel/Frame 029195/0048 →
MERGER Recorded Oct 25, 2012
From: ENTORIAN GP LLC
To: ENTORIAN TECHNOLOGIES INC.
Reel/Frame 029195/0114 →
CHANGE OF NAME Recorded Jan 26, 2010
From: STAKTEK GROUP, L.P.
To: ENTORIAN TECHNOLOGIES L.P.
Reel/Frame 023848/0062 →