Unidirectional error code transfer for a bidirectional data link

1. A mechanism, comprising:

a link interface, wherein the link interface is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information;

a first means for dynamically generating first error-detection information for at least a portion of write data;

a second means for transmitting the write data, wherein the second means is coupled to the link interface;

a first delay element coupled to an output from the first means;

a third means for receiving second error-detection information corresponding to at least the portion of the write data, wherein the third means is coupled to the link interface; and

error-detection logic coupled to an output from the first delay element and an output from the third means,

wherein the error-detection logic is to detect errors in at least the portion of the write data based on the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

2. The mechanism of claim 1 , further comprising means for performing a remedial action if the error condition is asserted.

3. A computer readable medium containing data representing a circuit that includes:

a link interface, wherein the link interface is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information;

a first encoder to dynamically generate first error-detection information for at least a portion of write data;

a first transmitter coupled to the link interface, wherein the first transmitter is to transmit the write data;

a first delay element coupled to an output from the first encoder;

a first receiver coupled to the link interface, wherein the first receiver is to receive second error-detection information corresponding to at least the portion of the write data; and

error-detection logic coupled to an output from the first delay element and an output from the first receiver,

wherein the error-detection logic is to detect errors in at least the portion of the write data based on the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

4. The computer readable medium of claim 3 , wherein the data representing the circuit further includes data representing logic to perform a remedial action if the error condition is asserted.

5. A memory system, comprising:

a memory device having device-side logic to generate device error detection codes for incoming write data and outgoing read data;

a controller having:

controller-side logic to generate controller error detection codes for outgoing write data and incoming read data,

a data transmitter that transmits write data to the memory device,

a data receiver that receives read data from the memory device, and

an error detection mechanism to detect errors for the write data and the read data based on the device error detection codes and the controller error detection codes; and

a bus interface coupling the controller and the memory device, including bi-directional data communication routing for carrying read data and write data, and a uni-directional error detection code link for transmitting the device error detection codes to the controller.

6. The system according to claim 5 , wherein the error detection mechanism includes an exclusive-or function that identifies mismatches between the device error detection codes and the controller error detection codes.

7. The system according to claim 5 , wherein each of the device-side logic and the controller-side logic generates horizontal data error detection codes.

8. The system according to claim 5 , wherein each of the device-side-logic and the controller-side logic generates vertical data error detection codes.

9. The system according to claim 5 , wherein the write data includes write mask data.

10. The system according to claim 5 , further comprising a retry mechanism that performs a memory operation retry upon detection of a mismatch between the device error correction codes and the controller error detection codes.

11. The system according to claim 5 ,

the memory device, further including:

first device-side logic to generate first error detection information for at least a portion of incoming write data, and

second device-side logic to generate second error detection information based on the first error detection information and at least a portion of outgoing read data; and

the memory controller, further including:

first controller-side logic to generate third error detection information for at least a portion of the outgoing write data,

second controller-side logic to generate fourth error detection information based on a delayed version of the third error detection information and at least a portion of the incoming read data,

the error detection mechanism to determine if the write data was received by the memory device without error and if the read data was received by the controller without error based on the fourth error detection information and the second error detection information.

12. A method of operating a controller, comprising:

dynamically generating first error-detection information for at least a portion of data, wherein the data is one of: outgoing write data and incoming read data;

when the data is write data,

receiving from a remote device, second error-detection information corresponding to at least the portion of the write data as received by the remote device, and

detecting errors in at least the portion of the write data based on the second error-detection information and a delayed version of the first error-detection information, and, if an error is detected, to assert a first error condition; and

when the data is read data,

receiving from the remote device, third error-detection information corresponding to at least the portion of the read data as transmitted by the remote device, and

detecting errors in at least the portion of the read data based on the third error-detection information and the first error-detection information, and, if an error is detected, to assert a second error condition.