Patent Assignment
Reel/Frame 073085/0650
Assignment of Assignor's Interest
Recorded: 2025-10-15
Pages: 12
Assignor
RAMBUS INC.
Executed: 2025-09-29
Assignee
SIGNAL LLP
1468 JAMES ROAD, GARDNERVILLE, NEVADA, 89460
Covered Properties
(142)
Multi-Die Memory Device
Dram Device with Built-in Self-Test Circuitry
Multi-Die Memory Device
Multi-Die Memory Device
Multi-Die Memory Device
Multi-Die Memory Device
Multi-Die Memory Device
Multi-Die Memory Device
Multi-Die Memory Device
Multi-Die Memory Device
Multi-Die Memory Device
Multi-Die Memory Device
Multi-Die Memory Device
Application:
18/657,631 →
Publication:
US 2024/0404580
Interface with Variable Data Rate
Interface with Variable Data Rate
Interface with Variable Data Rate
Interface with Variable Data Rate
Interface with Variable Data Rate
Interface with Variable Data Rate
Interface with Variable Data Rate
Interface with Variable Data Rate
Interface with Variable Data Rate
Memory System with Error Detection and Retry Modes of Operation
Memory System with Error Detection and Retry Modes of Operation
Memory System with Error Detection and Retry Modes of Operation
Memory System With Error Detection And Retry Modes Of Operation
Memory Chip with Error Detection and Retry Modes of Operation
Controller Device for Use with Electrically Erasable Programmable Memory Chip with Error Detection and Retry Modes of Operation
Memory Controller With Error Detection And Retry Modes Of Operation
Memory Controller With Error Detection And Retry Modes Of Operation
Memory Controller With Error Detection And Retry Modes Of Operation
Memory Controller With Error Detection And Retry Modes Of Operation
Memory Controller with Error Detection and Retry Modes of Operation
Application:
18/670,952 →
Publication:
US 2025/0004867
Integrated Circuit with Graduated on-Die Termination
Controlling Memory Devices That Have on-Die Termination
Memory-Module Buffer with on-Die Termination
Memory Controller That Controls Termination in a Memory Device
Integrated Circuit Device with Dynamically Selected on-Die Termination
Dynamic on-Die Termination Selection
Controlling Dynamic Selection of on-Die Termination
Controlling on-Die Termination in a Dynamic Random Access Memory Device
Multi-Valued on-Die Termination
Buffered Memory Module Having Multi-Valued on-Die Termination
Command-Triggered on-Die Termination
Nonvolatile Memory Device with on-Die Control and Data Signal Termination
Nonvolatile Memory Device with Time-Multiplexed, on-Die-Terminated Signaling Interface
Nonvolatile Memory with Chip-Select/Device-Address Triggered on-Die Termination
Nonvolatile Memory with Command-Driven on-Die Termination
Memory Device with Programmed Device Address and On-Die-Termination
Controlling on-Die Termination in a Nonvolatile Memory
Controlling a Flash Device Having Time-Multiplexed, On-Die-Terminated Signaling Interface
On-Die Termination Control
On-Die Termination Control
Memory Component with on-Die Termination
Transaction-Based on-Die Termination
On-Die Termination Control
Integrated Circuit That Applies Different Data Interface Terminations During and After Write Data Reception
Integrated Circuit That Applies Different Data Interface Terminations During and After Write Data Reception
Memory Controller with Staggered Request Signal Output
Memory Controller with Staggered Request Signal Output
Memory Controller with Staggered Request Signal Output
Integrated Circuit with Staggered Signal Output
Memory Controller with Staggered Request Signal Output
Memory Controller with Staggered Request Signal Output
Memory Controller with Staggered Request Signal Output
Memory Controller with Staggered Request Signal Output
Memory Controller with Staggered Request Signal Output
Memory Controller with Staggered Request Signal Output
Memory Device with Circuitry to Transmit Feedback Indicative of a Phase Relationship
Memory Controller with Staggered Request Signal Output
Memory Controller with Staggered Request Signal Output
System to Detect and Identify Errors in Control Information, Read Data and/or Write Data
Memory Error Detection
Memory Error Detection
Patent:
8,555,116 →
Application:
13/666,918 →
Memory Error Detection
Patent:
8,707,110 →
Application:
14/020,755 →
Memory Error Detection
Memory Error Detection
Memory Error Detection
Memory Error Detection
Memory Error Detection
Memory Error Detection
Memory error detection
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
On-Die Termination of Address and Command Signals
Application:
19/025,949 →
Publication:
US 2025/0226015
Memory Module Including a Plurality of Integrated Circuit Memory Devices and a Plurality of Buffer Devices in a Matrix Topology
System Including a Buffered Memory Module
Memory System Topologies Including a Buffer Device and an Integrated Circuit Memory Device
Memory System Topologies Including a Buffer Device and an Integrated Circuit Memory Device
Memory System Topologies Including a Buffer Device and an Integrated Circuit Memory Device
Memory System Topologies Including a Buffer Device and an Integrated Circuit Memory Device
Memory System Topologies Including a Buffer Device and an Integrated Circuit Memory Device
Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
Memory System Topologies Including a Buffer Device and an Integrated Circuit Memory Device
Memory System Topologies Including a Buffer Device and an Integrated Circuit Memory Device
Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
Memory System Topologies Including a Memory Die Stack
Memory System Topologies Including a Memory Die Stack
Memory System Topologies Including A Memory Die Stack
Memory System Topologies Including A Memory Die Stack
Unidirectional Error Code Transfer for a Bidirectional Data Link
Unidirectional Error Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link
Unidirectional Error Code Transfer Method for a Bidirectional Data Link
Unidirectional Error Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link
Unidirectional Error Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link
Unidirectional Error Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link
Memory Controller with Write Data Error Detection and Remediation
Electrically erasable programmable memory device that generates error-detection information
Electrically Erasable Programmable Memory Device That Generates a Cyclic Redundancy Check (Crc) Code
System and Module Comprising an Electrically Erasable Programmable Memory Chip
Memory Device with Retransmission Upon Error
Controller Device with Retransmission Upon Error
Controller That Receives a Cyclic Redundancy Check (Crc) Code from an Electrically Erasable Programmable Memory Device
Memory Device with Unidirectional Cyclic Redundancy Check (Crc) Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link
Controller That Receives a Cyclic Redundancy Check (Crc) Code for Both Read and Write Data Transmitted via Bidirectional Data Link
Memory device with unidirectional error detection code transfer for both read and write data transmitted via bidirectional data link
Controller That Receives a Cyclic Redundancy Check (Crc) Code for Both Read and Write Data Transmitted via Bidirectional Data Link
Controller That Receives a Cyclic Redundancy Check (Crc) Code for Both Read and Write Data Transmitted via Bidirectional Data Link
Remedial Action Indication
Controller That Receives a Cyclic Redundancy Check (Crc) Code for Both Read and Write Data Transmitted via Bidirectional Data Link
Application:
19/017,200 →
Publication:
US 2025/0245083
High-speed signaling systems with adaptable pre-emphasis and equalization
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
Related Assignments
(8)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 21, 2009
From: FRANS, YOHAN U.; LEE, HAE-CHANG; LEIBOWITZ, BRIAN S.; LI, SIMON
To: RAMBUS INC.
Reel/Frame 023687/0484 →
Assignment of Assignor's Interest
May 22, 2014
From: BEST, SCOTT C.; LI, MING
To: RAMBUS INC.
Reel/Frame 032952/0385 →
Assignment of Assignor's Interest
Oct 9, 2014
From: FRANS, YOHAN U.; LEE, HAE-CHANG; LEIBOWITZ, BRIAN S.; LI, SIMON
To: RAMBUS INC.
Reel/Frame 033921/0519 →
Assignment of Assignor's Interest
Jul 15, 2015
From: BEST, SCOTT C.; LI, MING
To: RAMBUS INC.
Reel/Frame 036101/0290 →
Assignment of Assignor's Interest
Nov 5, 2015
From: FRANS, YOHAN U.; LEE, HAE-CHANG; LEIBOWITZ, BRIAN S.; LI, SIMON
To: RAMBUS INC.
Reel/Frame 036972/0567 →
Assignment of Assignor's Interest
Apr 14, 2016
From: BEST, SCOTT C.; LI, MING
To: RAMBUS INC.
Reel/Frame 038286/0459 →
Assignment of Assignor's Interest
Sep 7, 2018
From: BEST, SCOTT C.; LI, MING
To: RAMBUS INC
Reel/Frame 046818/0264 →
Assignment of Assignor's Interest
Nov 16, 2019
From: BEST, SCOTT C.; LI, MING
To: RAMBUS INC
Reel/Frame 051030/0772 →