Memory error detection
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
1. A dynamic random access memory (DRAM) integrated circuit, comprising:
circuitry to receive, from a memory controller, an address with a write command that specifies a write operation;
circuitry to buffer the write command for an interval of time comprising a latency associated with time to perform the write operation and a time associated with detection of an error in the address; and
circuitry to cause the DRAM integrated circuit to preclude the write operation from being completed if an error is determined to exist in the address within the time associated with detection of an error in the address and to complete the write operation following expiration of the interval of time in absence of a determination that there is an error associated with the write command.
2. The DRAM integrated circuit of claim 1 , wherein the interval of time and the latency are each expressed as an integer number of clock cycles.
3. The DRAM integrated circuit of claim 2 , wherein the DRAM integrated circuit includes circuitry programmable by the memory controller during a start-up sequence to define the interval of time.
4. The DRAM integrated circuit of claim 2 , wherein said DRAM integrated circuit comprises circuitry to determine the interval of time during a start-up sequence.
5. The DRAM integrated circuit of claim 1 , wherein the DRAM integrated circuit is also to receive, from the memory controller, a read address with a read command that specifies a read operation, and wherein circuitry of the DRAM integrated circuit is to buffer the read command for an interval of time comprising a latency associated with time to perform the read operation and a time associated with detection of an error in the read address.
6. The DRAM integrated circuit of claim 1 , wherein the DRAM integrated circuit is to send information to the memory controller and the memory controller is to determine whether there is an error in the address.
7. The DRAM integrated circuit of claim 6 , wherein:
the information comprises an error detection code;
the DRAM integrated circuit comprises circuitry to calculate the error detection code; and
the circuitry to cause the DRAM integrated circuit to preclude the write operation from being completed if an error is determined to exist in the address within the time associated with detection of an error in the address, and to complete the write operation following expiration of the interval of time in absence of a determination that there is an error associated with the command, comprises circuitry to remove the write command from a queue resident in the DRAM integrated circuit responsive to an abort command from the memory controller.
8. The DRAM integrated circuit of claim 1 , wherein the DRAM integrated circuit is to permit completion of the write operation notwithstanding an error confined to write data associated with the write command.
9. The DRAM integrated circuit of claim 1 , wherein the DRAM integrated circuit further comprises circuitry to notify the memory controller responsive to an error in write data associated with the write command.
10. The DRAM integrated circuit of claim 1 , wherein:
the DRAM integrated circuit further comprises a queue to store at least one command from the memory controller subsequent to the write command;
the circuitry to cause the DRAM integrated circuit to preclude the write operation from being completed if an error is determined to exist in the address within the time associated with detection of an error in the address, and to complete the write operation following expiration of the interval of time in absence of a determination that there is an error associated with the command further comprises circuitry to discard from the queue a command of the at least one command from the memory controller subsequent to the write command if an error is determined to exist in the address within the time associated with detection of an error in the address; and
the DRAM integrated circuit is thereby operable to abort multiple commands, including the write command, if an error is determined to exist within the address within the time associated with detection of an error in the address.
11. A dynamic random access memory (DRAM) integrated circuit, comprising:
circuitry to receive, from a memory controller, an address with a write command that specifies a write operation;
circuitry to buffer the write command for an interval of time comprising a latency associated with time to perform the write operation and a time associated with detection of an error in the address;
circuitry to cause the DRAM integrated circuit to preclude the write operation from being completed if an error is determined to exist in the address within the time associated with detection of an error in the address and to complete the write operation following expiration of the interval of time in absence of a determination that there is an error associated with the command; and
circuitry programmable by the memory controller to store a value, the interval of time being dependent on the value.
12. The DRAM integrated circuit of claim 11 , wherein the interval of time is defined as an integer number of clock cycles.
13. The DRAM integrated circuit of claim 11 , wherein the DRAM integrated circuit is also to receive, from the memory controller, a read address with a read command that specifies a read operation, and wherein circuitry of the DRAM integrated circuit is also to buffer the read command for an interval of time comprising a latency associated with time to perform the read operation and an time associated with detection of an error in the read address.
14. The DRAM integrated circuit of claim 11 , wherein the DRAM integrated circuit is to send information to the memory controller and the memory controller is to determine whether there is an error in the address.
15. The DRAM integrated circuit of claim 14 , wherein:
the information comprises an error detection code;
the DRAM integrated circuit comprises circuitry to calculate the error detection code; and
the circuitry to cause the DRAM integrated circuit to preclude the write operation from being completed if an error is determined to exist in the address within the time associated with detection of an error in the address, and to complete the write operation following expiration of the interval of time in absence of a determination that there is an error associated with the command, comprises circuitry to remove the write command from a queue resident in the DRAM integrated circuit responsive to an abort command from the memory controller.
16. The DRAM integrated circuit of claim 11 , wherein the DRAM integrated circuit is to permit execution of the write command notwithstanding an error confined to write data associated with the write command.
17. The DRAM integrated circuit of claim 11 , wherein the DRAM integrated circuit further comprises circuitry to notify the memory controller responsive to an error in write data associated with the write command.
18. The DRAM integrated circuit of claim 11 , wherein:
the DRAM integrated circuit further comprises a queue to store at least one command from the memory controller subsequent to the write command;
the circuitry to cause the DRAM integrated circuit to preclude the write operation from being completed if an error is determined to exist in the address within the time associated with detection of an error in the address, and to complete the write operation following expiration of the interval of time in absence of a determination that there is an error associated with the command further comprises circuitry to discard from the queue a command of the at least one command from the memory controller subsequent to the write command if an error is determined to exist in the address within the time associated with detection of an error in the address; and
the DRAM integrated circuit is thereby operable to abort multiple commands, including the write command, if an error is determined to exist within the address within the time associated with detection of an error in the address.
19. A dynamic random access memory (DRAM) integrated circuit, comprising:
circuitry to receive, from a memory controller, an address with a write command that specifies a write operation;
a queue to store at least one command from the memory controller subsequent to the write command;
circuitry to buffer the write command for a number of clock cycles comprising a latency associated with time to perform the write operation and a time associated with detection of an error in the address; and
circuitry to cause the DRAM integrated circuit to preclude the write operation from being completed if an error is determined to exist in the address within the time associated with detection of error in the address and to complete the write operation following expiration of the number of clock cycles in absence of a determination that there is an error associated with the command, including circuitry to discard from the queue a command of the at least one command from the memory controller subsequent to the write command if an error is determined to exist in the address within the time associated with detection of error in the address.
20. The DRAM integrated circuit of claim 19 , wherein the DRAM integrated circuit is to permit completion of the write operation notwithstanding an error confined to write data associated with the write command.