Memory device with circuitry to transmit feedback indicative of a phase relationship
A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship between the control signal and the timing signal.
1. A memory device, comprising:
a first receive circuit to receive a control signal of a memory access request from a memory controller;
a second receive circuit to receive a timing signal from the memory controller; and
circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship between the control signal and the timing signal.
2. The memory device according to claim 1 , wherein the control signal is a chip select signal and the timing signal is a clock signal.
3. The memory device according to claim 1 , wherein:
the feedback is indicative of the phase relationship between the control signal and the timing signal as-received at the memory device.
4. The memory device according to claim 3 , wherein:
the feedback indicates whether a relative phase difference between the control signal and the timing signal should be adjusted by the memory controller.
5. The memory device according to claim 4 , wherein:
the feedback comprises first data accessed in response to the memory read request as received by the memory device; and
wherein a change to the phase relationship for a subsequent memory access request is based on the first data.
6. The memory device according to claim 5 , further comprising a plurality of receivers to receive the memory access request in response to the timing signal, wherein the control signal selects the memory device for the access.
7. The memory device according to claim 1 , embodied as a dynamic random access memory (DRAM) memory device.
8. A dynamic random access memory (DRAM) integrated circuit (IC) chip, comprising:
a first receive circuit to receive a chip select signal of a memory access request;
a second receive circuit to receive a clock signal; and
circuitry to transmit, during a calibration mode, feedback indicative of a phase relationship between the chip select signal and the clock signal.
9. The DRAM IC chip according to claim 8 , wherein:
the first receive circuit is to receive the chip select signal from a memory controller via a control signal path; and
the second receive circuit is to receive the clock signal from the memory controller via a timing signal path, wherein the chip select signal and the clock signal are driven from the memory controller with a relative phase offset, and wherein the relative phase offset compensates for a skew difference between the chip select signal propagating on the control signal path and the clock signal propagating on the timing signal path.
10. The DRAM IC chip according to claim 9 , wherein the relative phase offset of the chip select signal relative to the clock signal is based on relative loading between the control signal path and the timing signal path.
11. The DRAM IC chip according to claim 8 , further comprising:
a third receive circuit to receive command/address (C/A) signals from the memory controller, the C/A signals accompanying the chip select signal and the clock signal and arriving at the memory device in a predefined phase alignment with respect to the chip select signal and the clock signal.
12. The DRAM IC chip according to claim 8 , wherein the circuitry to transmit the feedback comprises:
a data input/output (I/O) driver to transmit the feedback to the memory controller.
13. The DRAM IC chip according to claim 8 , wherein:
the feedback comprises first data accessed in response to the memory access request as executed in accordance with the phase relationship between the chip select signal and the clock signal; and
wherein a change to the phase relationship for a subsequent memory access request is based on the first data.
14. The DRAM IC chip according to claim 13 , wherein:
the change to the phase relationship is based on a comparison of the first data to known data.
15. A dynamic random access memory (DRAM) integrated circuit (IC) memory device, comprising:
a first receive circuit to receive a chip select signal from a from an external control signal path, the chip select signal to select the memory device for a memory access;
a second receive circuit to receive a clock signal from an external timing signal path;
a third receive circuit to receive a memory access command synchronously with respect to the clock signal; and
circuitry to transmit, during a calibration mode, feedback along an external data path, the feedback indicative of a phase relationship between the chip select signal and the clock signal.
16. The DRAM IC memory device according to claim 15 , wherein the circuitry to transmit the feedback comprises:
a data driver to transmit the feedback to a memory controller.
17. The DRAM IC memory device according to claim 15 , wherein:
the feedback comprises first data accessed in response to a memory read request as; and
wherein a change to the phase relationship for a subsequent memory access request is based on the first data.
18. The DRAM IC memory device according to claim 17 , wherein:
the change to the phase relationship is based on a comparison of the first data to known data.
19. The DRAM IC memory device according to claim 15 , wherein the feedback indicates whether a relative phase difference between the control signal and the timing signal should be adjusted by a memory controller.
20. The DRAM IC memory device according to claim 15 , wherein:
the feedback is indicative of the phase relationship between the chip select signal and the clock signal as-received at the DRAM IC memory device.