Memory controller with staggered request signal output
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
1. A memory controller comprising:
request logic to generate a memory access request, the memory access request including command information and control information, the control information to enable a memory device to receive the command information; and
an output circuit to insert a timing offset between launch of the control information and launch of the command information to the memory device.
2. The memory controller according to claim 1 , wherein the command information is launched after the control information.
3. The memory controller according to claim 1 , further comprising:
storage circuitry to store a value;
a first output driver circuit to launch the control information to the memory device; and
a second output driver circuit to launch the command information with respect to the control information by the timing offset, the timing offset based on the value.
4. The memory controller according to claim 3 , wherein the value represents a relative time interval between launch times of the control information and command information.
5. The memory controller according to claim 3 , and further comprising:
a timing circuit to generate a timing reference signal; and
wherein the control information is launched via a timing relationship with the timing reference signal, and the value represents a time interval between launch of the command information and the timing reference signal.
6. The memory controller according to claim 3 , wherein:
the storage circuitry stores a second value representing a second timing offset between launch of the control information and the command information;
in a first mode, the predetermined time interval is based on the value; and
in a second mode, the predetermined time interval is based on the second value.
7. The memory controller according to claim 3 , wherein:
the storage circuitry comprises programmable register circuitry.
8. The memory controller according to claim 3 , wherein:
the storage circuitry comprises a look-up table.
9. A method of operation within a memory controller, the method comprising:
generating command information;
generating control information to enable a memory device to receive the command information;
inserting a timing offset between launch of the control information and the command information to the memory device.
10. The method according to claim 9 wherein the timing offset is in accordance with a first programmed value.
11. The method according to claim 10 , and further comprising:
storing the first programmed value in a programmable register.
12. The method according to claim 10 , and further comprising:
storing the first programmed value in a lookup table.
13. The method according to claim 10 , wherein inserting a timing offset comprises:
launching the control information; and
launching the command information at a timing relationship corresponding to the timing offset.
14. The method according to claim 13 , wherein:
the launching of the command information occurs after launching of the control information.
15. A method of operation in a memory controller, the method comprising:
in a first mode, launching control information with respect to command information in accordance with a first timing relationship; and
in a second mode, launching the control information with respect to the command information in accordance with a second timing relationship different from the first timing relationship, the second timing relationship including staggering launching of the command information with respect to launching of the control information.
16. The method according to claim 15 , wherein:
the first timing relationship is configured via a nominal default setting.
17. The method according to claim 16 , wherein:
the second timing relationship is defined by a timing offset value stored in programmable storage and based on a system topology.
18. A memory controller comprising:
request logic operative to
in a first mode, launch control information with respect to command information in accordance with a first timing relationship, and
in a second mode, launch control information with respect to command information in accordance with a second timing relationship different from the first timing relationship,
wherein the request logic includes circuitry to stagger launch of the command information with respect to launch of the control information.
19. The memory controller according to claim 18 and further comprising:
storage circuitry to store nominal default values that define the first timing relationship.
20. The memory controller according to claim 19 wherein:
the storage circuitry stores a programmable timing offset value that defines the second timing relationship, the programmable timing offset value based on a system topology.