Memory controller with staggered request signal output
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
1. A memory controller comprising:
a memory interface for communicating with a memory device at a signaling rate;
a timing control circuit having inputs to receive respective first and second signal components of a memory access request, the timing circuit having outputs to launch the respective first and second signal components at times that are staggered to define an offset; and
wherein a value of the offset is based on the signaling rate.
2. The memory controller of claim 1 , wherein the timing control circuit indirectly establishes the offset.
3. The memory controller of claim 2 , wherein the timing control circuit includes:
a first timing element to establish a first timing offset representing a first time difference between a reference clock and a first timing signal used to launch the first signal component; and
a second timing element to establish a second timing offset representing a second time difference between the reference clock and a second timing signal used to launch the second signal component;
wherein the value of the offset is a sum of the first and second timing offsets.
4. The memory controller of claim 1 , wherein the timing control circuit directly establishes the offset.
5. The memory controller of claim 4 , wherein the timing control circuit includes:
a timing element to establish a timing offset representing a time difference between a first timing signal used to launch the first signal component and a second timing signal used to launch the second signal component.
6. The memory controller of claim 1 , wherein the first signal component comprises a memory control signal, and the second signal component comprises a command/address signal.
7. The memory controller of claim 1 , further including storage to store the offset value.
8. The memory controller of claim 7 , wherein the storage stores plural offset values mapped to plural signaling rates.
9. The memory controller of claim 7 , wherein the storage comprises a programmable register.
10. A method of operation in a memory controller, the method comprising:
interfacing with a memory device at a signaling rate;
launching a first component of a memory access request to the memory device;
launching a second component of the memory access request to the memory device, wherein a time difference between launch of the first component and launch of the second component defines an offset; and
wherein a value of the offset is based on the signaling rate.
11. The method of claim 10 , further comprising:
directly establishing the offset.
12. The method of claim 11 , wherein directly establishing the offset comprises:
programmably selecting a timing offset representing a time difference between a first timing signal used to launch the first component and a second timing signal used to launch the second component.
13. The method of claim 10 , further comprising:
indirectly establishing the offset.
14. The method of claim 13 , wherein indirectly establishing the offset comprises:
programmably selecting a first timing offset representing a first time difference between a reference clock and a first timing signal used to launch the first component; and
programmably selecting a second timing offset representing a second time difference between the reference clock and a second timing signal used to launch the second component.
15. The method of claim 10 , further comprising:
accessing storage to identify the offset value.
16. The method of claim 10 , wherein the offset value is specified in terms of absolute time.
17. The method of claim 10 , wherein accessing storage comprises:
retrieving the offset value from a look-up table, the look-up table having plural timing offset values correlated to plural signaling rates.
18. An integrated circuit (IC) device comprising:
a memory interface to communicate with a memory device at a signaling rate;
storage to store a timing offset based on the signaling rate; and
a timing circuit to stagger launch of a second memory request signal component with respect to a launch of a first memory request signal component, the staggered launch corresponding to the timing offset.
19. The IC device of claim 18 , wherein the IC device comprises a memory controller.
20. The IC device of claim 18 , wherein the timing offset is loaded into the storage during an initialization operation.