Memory error detection
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
1. A first integrated circuit, comprising:
at least one interface to receive data, a write command to write the data in to a memory, and an address associated with the memory for writing of the data;
a buffer to queue performance of the write command;
circuitry to generate error detection information based on the address and to transmit the error detection information to a second integrated circuit;
circuitry to abort the write command in response to an abort command received by the first integrated circuit; and
circuitry to convey the data from the buffer to the memory to perform the write command if the abort command is not received by the first integrated circuit.
2. The first integrated circuit of claim 1 , where the error detection information is based on both of (a) the address and (b) data to be exchanged with the second integrated circuit in association with a memory transaction.
3. The first integrated circuit of claim 2 , where the memory transaction is a first memory transaction and where the write command represents a second memory transaction, such that the error detection information is dependent on data and address information from different, respective memory transactions.
4. The first integrated circuit of claim 3 , where the circuitry to generate error detection information and to transmit the error detection information is to generate and transmit error detection information for each memory transaction, with each transmission of error detection information representing data and address information associated with respective memory transactions.
5. The first integrated circuit of claim 3 , where the error detection information comprises a cyclic redundancy code (CRC).
6. The first integrated circuit of claim 1 , where:
the first integrated circuit further comprises the memory and is embodied as a dynamic random access memory (DRAM) device; and
the data and at least part of the write command are received at different times.
7. The first integrated circuit of claim 1 , where the circuitry to convey the data from the buffer to the memory if the abort command is not received by the first integrated circuit is further to convey the data upon receipt of a commit command from the second integrated circuit.
8. The first integrated circuit of claim 1 , where the circuitry to convey the data from the buffer to the memory if the abort command is not received by the first integrated circuit is to automatically convey the data from the buffer to the memory if the abort command is not received within a predetermined period.
9. The first integrated circuit of claim 8 , where the predetermined period is no less than the sum of a time associated with derivation of the error detection information by the first integrated circuit, a round-trip travel time between the first and second integrated circuits and a time associated with processing of the error detection information by the second integrated circuit.
10. The first integrated circuit of claim 8 , where the predetermined period is programmable, and where the first integrated circuit further comprises circuitry to determine the predetermined period and to program a corresponding buffer latency during a startup sequence of the first integrated circuit.
11. The first integrated circuit of claim 1 , where the at least one interface comprises a first interface to receive both of the write command and the abort command from a command bus.
12. The first integrated circuit of claim 1 , where the buffer is to queue performance of the write command for a period that represents deliberately injected latency sufficient for a remote error determination that encompasses the address.
13. A dynamic random access memory (DRAM) integrated circuit, comprising:
a memory array comprising DRAM cells;
at least one interface to receive data, a write command to write the data in to the memory array, and a row address and a column address for writing of the data;
a buffer to buffer the write command for a period that represents deliberately injected latency sufficient for a remote error determination that encompasses the row address and column address;
circuitry to generate error detection information for the row address and the column address and to transmit the error detection information to a memory controller integrated circuit for the remote error determination;
circuitry to abort the write command in response to an abort command received by the DRAM integrated circuit from the memory controller integrated circuit; and
circuitry to write the data into the memory array if the abort command is not received by the memory integrated circuit within the period;
where the data and at least part of the write command are received at different times.
14. The DRAM integrated circuit of claim 13 , further comprising first and second mutually-exclusive groups of at least one external electrical contact, the first mutually-exclusive group to transmit the error detection information to the memory controller integrated circuit via an error bus, the second mutually-exclusive group to receive commands, including the write command and the abort command, from the memory controller integrated circuit.
15. The DRAM integrated circuit of claim 13 , where the period is no less than the sum of a time associated with derivation of the error detection information by the first integrated circuit, a round-trip travel time between the first and second integrated circuits and a time associated with processing of the error detection information by the second integrated circuit.
16. The DRAM integrated circuit of claim 13 , where the period is programmable, and where the DRAM integrated circuit comprises circuitry to store a value representing a buffer latency period that transpires during a startup sequence of the DRAM integrated circuit.
17. The DRAM integrated circuit of claim 13 , where:
the write command corresponds to a first memory transaction; and
the error detection information is based on both of the address associated with the write command and data to be exchanged with the second integrated memory circuit in association with a second memory transaction, such that the error detection information is dependent on data and address information from different, respective memory transactions.
18. A method of operating a memory integrated circuit, comprising:
receiving a write command to write the data in a memory array of the memory integrated circuit, and receiving data and a row address and a column address for writing of the data;
buffering the write command for a period that represents deliberately injected latency sufficient for a remote error determination that encompasses the row address and the column address;
using error detection circuitry to generate error detection information for the row address and the column address for the remote error determination;
transmitting the error detection information to a memory controller integrated circuit for the remote error determination;
aborting the write command in response to an abort command received from the memory controller integrated circuit; and
issuing the write command to write the data into the memory array if the abort command is not received within the period.
19. The method of claim 18 , where:
the write command corresponds to a first memory transaction; and
the error detection information is based on both of the address associated with the write command and data to be exchanged with the second integrated memory circuit in association with a second memory transaction, such that the error detection information is dependent on data and address information from different, respective memory transactions.
20. The method of claim 19 ,
where using the error detection circuitry to generate the error detection information and transmitting the error detection information to the memory controller includes generating the error detection information for each memory transaction and, for each memory transaction, transmitting error detection information representing data and address information associated with respective memory transactions.