Multi-die memory device
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
1. An integrated circuit (IC), comprising:
a configurable-width data interface to transfer data, the configurable-width data interface being configurable to operate at a selectable first width or a selectable second width that is different than the first width, the configurable-width data interface for coupling to:
a first memory die of a set of memory dies connected using via signal paths that are formed in the set of memory dies; and
a second memory die of the set of memory dies connected using the via signal paths.
2. The IC of claim 1 , wherein:
a selection between the first width or the second width is based on a mode value.
3. The IC of claim 2 , wherein:
the mode value is retrieved from storage.
4. The IC according to claim 2 , wherein:
the mode value is provided to the IC from an external source.
5. The IC according to claim 1 , realized as a logic IC die.
6. The IC according to claim 5 , wherein:
the set of memory dies is disposed in a stacked relationship with the logic IC die.
7. The IC according to claim 1 , wherein:
the set of memory dies comprise dynamic random access memory (DRAM) memory dies.
8. The IC according to claim 1 , wherein:
the configurable-width data interface is to couple to one of the first memory die or the second memory die, using the via signal paths, in response to a device-select signal.
9. An integrated circuit (IC) chip, comprising:
circuitry to transfer data via a configurable-width data interface between the IC chip and a stack of dynamic random access memory (DRAM) memory chips, the stack of DRAM memory chips interconnected using via signal paths that are formed in the stack of DRAM memory chips;
wherein the configurable-width data interface being configurable to operate at a selectable first width or a selectable second width that is different than the first width.
10. The IC chip of claim 9 , wherein:
a selection between the first width or the second width is based on a mode value.
11. The IC chip according to claim 10 , wherein:
the mode value is retrieved from storage.
12. The IC chip according to claim 10 , wherein:
the mode value is provided to the IC from an external source.
13. The IC chip according to claim 9 , realized as a logic IC chip.
14. The IC chip according to claim 13 , wherein:
the stack of DRAM memory chips is disposed in a stacked relationship with the logic IC chip.
15. The IC according to claim 9 , wherein:
the circuitry to transfer data is to couple to a first DRAM memory chip of the stack of DRAM memory chips, using the via signal paths, in response to a device-select signal.
16. A method of operation in an integrated circuit (IC) device, the method comprising:
configuring a data interface for coupling to
a first memory die of a set of memory dies connected using via signal paths formed in the set of memory dies;
a second memory die of the set of memory dies connected using the via signal paths;
wherein the configuring includes selecting for operation a first width or a second width that is different than the first width.
17. The method according to claim 16 , wherein:
the selecting is based on a mode value.
18. The method according to claim 17 , further comprising:
retrieving the mode value from storage.
19. The method according to claim 17 , further comprising:
receiving the mode value from an external source.
20. The method according to claim 16 , further comprising:
receiving a device-select signal; and
coupling the data interface to one of the first memory die or the second memory die in response to the device-select signal.