Multi-die memory device
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
1. An integrated circuit, comprising:
circuitry to transmit:
a first set of address values for facilitating a first memory transaction with a first independently accessible memory die of a set of memory dies connected using through-silicon-via (TSV) signal paths;
a second set of address values for facilitating a second memory transaction with a second independently accessible memory die of the set of memory dies connected using the TSV signal paths; and
a signal for use in selecting a memory die of the set of memory dies connected using the TSV signal paths.
2. The integrated circuit of claim 1 , wherein:
the set of memory dies comprises solely the first independently accessible memory die and the second independently accessible memory die.
3. The integrated circuit of claim 1 , wherein:
the set of memory dies includes the first independently accessible memory die, the second independently accessible memory die, and at least a third independently accessible memory die.
4. The integrated circuit according to claim 1 , wherein:
each of the first and second independently accessible memory die include multiple banks; and
wherein the first and second sets of address values include bank address values to specify one of the multiple banks of each of the first and second independently accessible memory die for each memory transaction.
5. The integrated circuit according to claim 1 , further comprising:
circuitry to receive the first and second sets of address values and the signal from a memory controller.
6. The integrated circuit according to claim 1 , wherein:
the circuitry is to transmit the signal in the form of a device-select signal.
7. The integrated circuit according to claim 1 , wherein:
the circuitry is configured to communicate with the selected memory die via a dynamic random access memory (DRAM) protocol.
8. An integrated circuit (IC) chip for communicating with a stacked dynamic random access memory (DRAM) device, comprising:
circuitry to transmit:
a first set of address values for facilitating a first memory transaction with a first independently accessible memory die of the stacked DRAM device using through-silicon-via (TSV) signal paths;
a second set of address values for facilitating a second memory transaction with a second independently accessible memory die of the stacked DRAM device using the TSV signal paths; and
a device-select signal for use in selecting a memory die of the stacked DRAM device using the TSV signal paths.
9. The IC chip of claim 8 , wherein:
the stacked DRAM device comprises solely the first independently accessible memory die and the second independently accessible memory die.
10. The IC chip of claim 8 , wherein:
the stacked DRAM device includes the first independently accessible memory die, the second independently accessible memory die, and at least a third independently accessible memory die.
11. The IC chip according to claim 8 , wherein:
each of the first and second independently accessible memory die include multiple banks; and
wherein the first and second sets of address values include bank address values to specify one of the multiple banks of each of the first and second independently accessible memory die for each memory transaction.
12. The IC chip according to claim 8 , wherein:
the first and second sets of address values are each associated with independent sets of command, address and write data signals.
13. The IC chip according to claim 8 , wherein:
the first and second sets of address values are serialized for transfer to the selected memory die.
14. The IC chip according to claim 8 , embodied as a DRAM memory controller.
15. A method of operation in an integrated circuit, the method comprising:
transferring a first set of address values for facilitating a first memory transaction with a first independently accessible memory die of a set of memory dies connected using through-silicon-via (TSV) signal paths;
transferring a second set of address values for facilitating a second memory transaction with a second independently accessible memory die of the set of memory dies connected using the TSV signal paths; and
transferring a signal for use in selecting a memory die of the set of memory dies connected using the TSV signal paths.
16. The method according to claim 15 , wherein the transferring of the signal comprises:
transferring a device-select signal for use in selecting the memory die of the set of memory dies connected using the TSV signal paths.
17. The method according to claim 15 , wherein the set of memory dies includes solely the first independently accessible memory die and the second independently accessible memory die, and wherein the transferring of the signal comprises:
transmitting the signal for use in selecting a memory die of the first or second independently accessible memory dies.
18. The method according to claim 15 , wherein the set of memory dies further includes at least a third independently accessible memory die, and wherein the transferring of the signal comprises:
transmitting the signal for use in selecting a memory die of the first, second or at least third independently accessible memory dies of the set of memory dies.
19. The method according to claim 15 , further comprising:
serializing the first and second sets of address signals for transfer to the selected memory die.
20. The method according to claim 15 , wherein each of the first and second independently accessible memory die include multiple banks, and wherein the method further comprises:
transmitting a bank address for each of the first and second sets of address values, each bank address specifying one of the multiple banks of each of the first and second independently accessible memory die for each memory transaction.