Memory system topologies including a buffer device and an integrated circuit memory device
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
1. A memory controller to control the operation of an external memory module, the memory controller comprising:
a circuit to receive configuration information from non-volatile storage of the external memory module, the configuration information representing presence of a plurality of memory die stacks disposed on the external memory module; and
an interface to transmit, as part of a memory access operation,
a memory access command to specify a memory access,
a chip select signal to select the memory die stacks for the memory access; and
information representing selection of a particular die within each die stack of the plurality of memory die stacks.
2. The memory controller of claim 1 , wherein the non-volatile storage comprises a serial presence detect (SPD) register, and wherein circuit to receive the configuration information is to access the SPD register.
3. The master of claim 1 , wherein the configuration information comprises values representing timing parameters of the plurality of memory die stacks, wherein the timing parameters include row access time, column access time, time between accesses to successive rows, and time between accesses to successive columns, and wherein the memory controller transmits memory access command timed according to the timing parameters.
4. The memory controller of claim 1 , wherein the information representing selection of a particular die within each die stack of the plurality of die stacks comprises one or more bits, wherein the one or more bits are to effectuate selection of the particular die within each die stack of the plurality of memory die stacks with each memory access command.
5. The memory controller of claim 4 , wherein the one or more bits are included in a row address provided with the memory access command to each die stack of the plurality of memory die stacks.
6. The memory controller of claim 1 , wherein the interface is to transmit a row address to activate a row in the particular die within each die stack of the plurality of memory die stacks, wherein the information representing selection of the particular die is provided with the row address.
7. The memory controller of claim 1 , wherein the particular die in each die stack of the plurality of memory die stacks provides a respective slice of data as part of the memory access operation.
8. The memory controller of claim 1 , wherein the configuration information specifies a number of memory dies within each die stack of the plurality of memory die stacks.
9. A method of operation of a memory controller, the memory controller to control the operation of memory dies disposed on an external memory module, the method comprising:
receiving configuration information from non-volatile storage of the external memory module, the configuration information representing presence of a plurality of memory die stacks disposed on the external memory module; and
as part of a memory access operation, transmitting,
a memory access command to specify a memory access,
a chip select signal to select the memory die stacks for the memory access, and
information representing selection of a particular die within each die stack of the plurality of memory die stacks.
10. The method of claim 9 , wherein the configuration information specifies a number of memory dies within each die stack of the plurality of memory die stacks.
11. The method of claim 9 , wherein receiving configuration information is performed during an initialization sequence.
12. The method of claim 9 , wherein the configuration information comprises values representing timing parameters of the plurality of memory die stacks, wherein transmitting the memory access command comprises transmitting the memory access command according to the timing parameters.
13. The method of claim 12 , wherein the timing parameters include row access time, column access time, time between accesses to successive rows, and time between accesses to successive columns of the plurality of memory dies.
14. The method of claim 9 , wherein the information representing selection of a particular die within each die stack of the plurality of memory die stacks comprises one or more bits, wherein the one or more bits are to effectuate selection of the particular die within each die stack of the plurality of memory die stacks with each memory access command.
15. The method of claim 14 , further comprising transmitting a row address to the plurality of memory die stacks, wherein the wherein the one or more bits are included in the row address.
16. The method of claim 9 , further comprising transmitting a row address to activate a row in the particular die in each stack of the plurality of memory die stacks, wherein the information representing selection of the particular die is transmitted with the row address.
17. The method of claim 9 , wherein the particular die in each die stack of the plurality of memory die stacks provides a respective slice of data as part of the memory access operation.
18. A memory controller to control the operation of a plurality of memory die stacks, the memory controller comprising:
a circuit to receive configuration information representing a number of memory die within each stack of the plurality of memory die stacks; and
an interface to transmit to the plurality of memory die stacks, as part of a memory access operation,
a memory access command to specify a memory access,
a chip select signal to select the memory die stacks for the memory access, and
information representing selection of a particular die within each die stack of the plurality of memory die stacks.
19. The memory controller of claim 18 , wherein the configuration information is to be received from non-volatile storage of an external memory module containing the plurality of memory die stacks.
20. The memory controller of claim 19 , wherein the information representing selection of a particular die within each die stack of the plurality of memory die stacks comprises one or more bits, wherein the one or more bits are to effectuate selection of the particular die within each die stack of the plurality of memory die stacks with each memory access command.