Memory system topologies including a buffer device and an integrated circuit memory device
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
1. A memory module comprising:
a memory die stack having a number of memory dies, the number being at least two, each of the memory dies having one or more dynamic random access memory (DRAM) arrays;
buffer circuitry to provide commands and associated addresses received from a memory controller to each of the memory dies, wherein said buffer circuitry is to also buffer exchange of data between the memory controller and a selected one of the memory dies; and
non-volatile storage to store configuration information, the configuration information including information identifying the number of memory dies in the memory die stack;
wherein the memory dies in the memory die stack are to be accessed by the memory controller according to the configuration information.
2. The memory module of claim 1 , wherein the non-volatile storage comprises a serial presence detect (SPD) register, and wherein said SPD register is readable by the memory controller.
3. The memory module of claim 1 , wherein the memory module is to connect to the memory controller via an external data bus having a first width, wherein the each of the memory dies comprises banks, wherein the buffer circuitry is adapted to transfer data to and from each of the banks using an internal data bus having a second width, different than the first width, wherein the configuration information comprises information identifying a relationship between the first width and the second width, and wherein the buffer circuitry is to be adapted as a function of the information identifying the relationship between the first width and the second width, so as to perform data transfer between the internal data bus and the external data bus.
4. The memory module of claim 1 , wherein the memory module is to connect to the memory controller via an external data bus according to a first serialization parameter, wherein the each of the memory dies comprises banks and the buffer circuitry is to transfer data to and from each of the banks using an internal data bus according to a second serialization parameter, different than the first serialization parameter, wherein the configuration information comprises information identifying a relationship between the first serialization parameter and the second serialization parameter, and wherein the buffer circuitry is to be adapted as a function of the information identifying the relationship between the first serialization parameter and the second serialization parameter, so as to perform data transfer between the banks and the memory controller.
5. The memory module of claim 1 , wherein the memory module is to connect to the memory controller via an external data bus, wherein the buffer circuitry is to connect to the memory dies using internal data buses respective to each of the memory dies, wherein the buffer circuitry is to transfer data between the memory controller and the selected one of the memory dies using the external data bus, and wherein the buffer circuitry is to transfer data between the memory controller and each selected one of the memory dies using the internal data bus respective to the selected one of the memory dies.
6. The memory module of claim 1 , wherein each of the memory dies is to form part of a respective rank of memory, and wherein said memory module is to transfer data between the memory controller and respective ranks of memory on consecutive cycles of a periodic timing signal, such that said memory module does not require an idle period of a data bus between accesses of respective ranks of memory, wherein said data bus is to be used to exchange data between the memory controller and each of the respective ranks.
7. The memory module of claim 1 , wherein the non-volatile storage is to store a value of a timing parameter comprising at least one of a row access time, a column access time, a time between accesses to successive rows, or a time between accesses to successive columns, and wherein the non-volatile storage is accessible by the memory controller to provide said value to the memory controller.
8. The memory module of claim 1 , wherein the non-volatile storage is to store a binary code, wherein each possible value of the binary code is mapped to a respective value of a time parameter to be used in accessing said memory dies, and wherein at least one of the memory controller or the buffer circuitry is to access said binary code in order to configure access to the memory dies.
9. The memory module of claim 1 , wherein:
the memory module further comprises
a set of one or more lines to identify the selected one of the memory dies couples the buffer circuitry and each of the memory dies, and
an internal command bus couples the buffer circuitry and each of the memory dies; and
the buffer circuitry is to receive data access commands from the memory controller and is to control the set of one or more lines so as to control the selected one of the memory dies as a function of one or more bits provided with each data access command received from the memory controller.
10. The memory module of claim 1 , further comprising an integrated circuit that packages the memory dies in common.
11. The memory module of claim 1 , further comprising a respective point-to-point data bus coupling the buffer circuitry and each of the memory dies.
12. A memory module comprising:
a memory die stack having a number of memory dies, the number being at least two, each of the memory dies having one or more dynamic random access memory (DRAM) arrays;
buffer circuitry to provide commands and associated addresses received from a memory controller to the memory dies, wherein said buffer circuitry is to also buffer exchange of data between the memory controller and a selected one of the memory dies; and
non-volatile storage to store configuration information, the configuration information including information identifying the number of memory dies in the memory die stack;
wherein the memory dies in the memory die stack are to be accessed by the memory controller according to the configuration information; and
wherein each of the memory dies is to form part of a respective rank of memory.
13. The memory module of claim 12 , wherein said memory module is to transfer data between the memory controller and the respective ranks of memory on consecutive cycles of a periodic timing signal, such that said memory module does not require an idle period of a data bus between accesses of respective ranks of memory, wherein said data bus is to be used to exchange data between the memory controller and each of the respective ranks.
14. The memory module of claim 12 , wherein the memory module is to connect to the memory controller via an external data bus having a first width, wherein the each of the memory dies comprises banks, wherein the buffer circuitry is adapted to transfer data to and from each of the banks using an internal data bus having a second width, different than the first width, wherein the configuration information comprises information identifying a relationship between the first width and the second width, and wherein the buffer circuitry is to be adapted as a function of the information identifying the relationship between the first width and the second width, so as to perform data transfer between the internal data bus and the external data bus.
15. The memory module of claim 12 , wherein the memory module is to connect to the memory controller via an external data bus according to a first serialization parameter, wherein the each of the memory dies comprises banks and the buffer circuitry is to transfer data to and from each of the banks using an internal data bus according to a second serialization parameter, different than the first serialization parameter, wherein the configuration information comprises information identifying a relationship between the first serialization parameter and the second serialization parameter, and wherein the buffer circuitry is to be adapted as a function of the information identifying the relationship between the first serialization parameter and the second serialization parameter, so as to perform data transfer between the banks and the memory controller.
16. The memory module of claim 12 , wherein the non-volatile storage is to store a value of a timing parameter comprising at least one of a row access time, a column access time, a time between accesses to successive rows, or a time between accesses to successive columns, and wherein the non-volatile storage is accessible by the memory controller to provide said value to the memory controller.
17. The memory module of claim 12 , wherein the non-volatile storage is to store a binary code, wherein each possible value of the binary code is mapped to a respective value of a time parameter to be used in accessing said memory dies, and wherein at least one of the memory controller or the buffer circuitry is to access said binary code in order to configure access to the memory dies.
18. The memory module of claim 12 , wherein:
the memory module further comprises
a set of one or more lines to identify the selected one of the memory dies, the set of one or more lines coupling the buffer circuitry and each of the memory dies, and
an internal command bus couples the buffer circuitry and each of the memory dies; and
the buffer circuitry is to receive data access commands from the memory controller and is to control the set of one or more lines so as to control the selected one of the memory dies as a function of one or more bits provided with each data access command received from the memory controller.
19. The memory module of claim 12 , further comprising a respective point-to-point data bus coupling the buffer circuitry and each of the memory dies.
20. A memory module comprising:
an integrated circuit having a number of memory dies arranged as a memory die stack, the number being at least two, each of the memory dies having one or more dynamic random access memory (DRAM) arrays;
buffer circuitry to provide commands and associated addresses received from a memory controller to each of the memory dies, wherein said buffer circuitry is to also buffer exchange of data between the memory controller and a selected one of the memory dies;
a respective point-to-point internal data bus coupling the buffer circuitry and each of the memory dies; and
non-volatile storage to store configuration information, the configuration information including information identifying the number of memory dies in the memory die stack, wherein the memory dies in the memory die stack are to be accessed by the memory controller according to the configuration information;
wherein the memory module further comprises
a set of one or more lines to identify the selected one of the memory dies, the set of one or more lines coupling the buffer circuitry and each of the memory dies, and
an internal command bus couples the buffer circuitry and each of the memory dies; and
wherein the buffer circuitry is to receive data access commands from the memory controller and is to control the set of one or more lines so as to control the selected one of the memory dies as a function of one or more bits provided with each data access command received from the memory controller.