IP Library › Granted Patent US 12,394,471
Granted Patent B2
US 12,394,471 · App. 18/340,726 · Granted Aug 19, 2025

Memory system topologies including a memory die stack

Inventors: Ian Shaeffer (Los Gatos, CA); Ely Tsern (Los Altos, CA); Craig Hampel (Los Altos, CA)
Assignee: Rambus Inc.
G11C11/4093G06F13/16G06F13/4027G06F13/4068G11C5/025G11C5/04G11C5/06G11C7/1006G11C7/222G11C11/4076G11C11/4091G11C11/4094G11C11/4096H01L25/0652H01L25/105G11C7/22H01L24/73H01L25/0657H01L25/18H01L2224/32145H01L2224/48227H01L2224/73265H01L2225/1005H01L2225/1023H01L2225/1058H01L2924/14H01L2924/15192H01L2924/15311H01L2924/15331H01L2924/3011H01L2924/3025
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Quick Facts
Patent No.
US 12,394,471
App. No.
18/340,726
Granted
Aug 19, 2025
Kind
B2
Abstract

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

Claims (33)

1. A memory controller for controlling a device having memory dies in a stack configuration, the memory controller comprising:

an interface to transmit to the device a command and a signal selecting the device, the command having multiple bit values; and

circuitry to format the multiple bit values of the command so as to select a memory die of the memory dies in the stack configuration, for a memory access;

wherein the memory dies in the stack configuration comprise a first die stack, wherein the memory controller is to control a second die stack comprising memory dies, each of first die stack and the second die stack corresponding to a respective slice of data, wherein a memory transaction that specifies the memory access is to select a memory die within each of the first die stack and the second die stack in connection with exchange of the respective slice of data, wherein the signal is a first chip select signal, and wherein the interface is to transmit to a second chip select signal to select the second die stack for the memory access.

2. The memory controller of claim 1 , wherein the command comprises a row address, the row address to activate a row in the selected memory die.

3. The memory controller of claim 1 , wherein the selected memory die in each of the first die stack and the second die stack provides a respective slice of data as part of the memory access operation.

4. The memory controller of claim 1 , wherein the device further comprises a serial presence detect (SPD) register, and wherein the memory controller comprises circuitry to receive information from the SPD register, wherein the memory controller is to configure at least one circuit dependent on the received information.

5. The memory controller of claim 4 , wherein the each selected memory die is to exchange read and write data according to a first interface standard, and wherein:

the memory controller comprises a data interface is to exchange data with the device according to a second interface standard, wherein the information received from the SPD register includes information representing the first interface standard; and

the memory controller comprises circuitry to program information into the device to cause the device to convert the read and write data between the first interface standard and the second interface standard.

6. The memory controller of claim 4 , wherein the memory controller comprises circuitry to determine a timing difference between accesses to different ones of the memory dies in the stack configuration, and circuitry to program information representing the timing difference into circuitry on the device for use in exchanging data with the different ones of the memory dies.

7. The memory controller of claim 4 , wherein the received information comprises values representing timing parameters, wherein the timing parameters include row access time, column access time, time between accesses to successive rows, and time between accesses to successive columns, and wherein the interface is to, in a manner timed according to the timing parameters, perform at least one of transmission of at least one the command to the device or transfer with the device of associated data.

8. The memory controller of claim 4 , wherein the received information specifies a number of the memory dies in the stack configuration.

9. The memory controller of claim 1 , wherein the memory controller further comprises circuitry to program information into a register on the device, an access to eachthe selected memory die to be performed by the device according to the information programmed into the register by the memory controller.

10. The memory controller of claim 1 , wherein:

the device comprises an interface and circuitry to communicate with each of the memory dies of the stack configuration via a shared data path having links; and

the memory controller further comprises circuitry to program the device, so as to configure data transfer between the interface of the device and the memory dies in the stack configuration according to a selective data path width, the selective data path width capable of being defined such that data is transferred over less than all of the links of the shared data path.

11. A method of operating a memory controller to control a device having memory dies in a stack configuration, the method comprising:

causing an interface of the memory controller to transmit to the device a command and a signal selecting the device, the command having multiple bit values; and

causing circuitry of the memory controller to format the multiple bit values of the command so as to select a memory die of the memory dies in the stack configuration, for a memory access;

wherein the memory dies in the stack configuration comprise a first die stack, wherein the method further comprises causing the memory controller to control a second die stack comprising memory dies, each of first die stack and the second die stack corresponding to a respective slice of data, wherein a memory transaction that specifies the memory access is to select a memory die within each of the first die stack and the second die stack in connection with exchange of the respective slice of data, wherein the signal is a first chip select signal, and wherein the method further comprises causing the interface to transmit to a second chip select signal, to select the second die stack, for the memory access.

12. The method of claim 11 , wherein the device further comprises a serial presence detect (SPD) register, and wherein the method further comprises causing circuitry of the memory controller to receive information from the SPD register and to configure at least one circuit dependent on the received information.

13. The method of claim 12 , wherein eachthe selected memory die is to exchange read and write data according to a first interface standard, and wherein:

the method further comprises causing a data interface of the memory controller to exchange data with the device according to a second interface standard, wherein the information received from the SPD register includes information representing the first interface standard; and

the method further comprises causing circuitry of the memory controller to program information into the device to cause the device to convert the read and write data between the first interface standard and the second interface standard.

14. The method of claim 12 , further comprising causing circuitry of the memory controller to determine a timing difference between accesses to different ones of the memory dies in the stack configuration, and to program information representing the timing difference into circuitry on the device for use in exchanging data with the different ones of the memory dies.

15. The method of claim 12 , wherein the received information comprises values representing timing parameters, wherein the timing parameters include row access time, column access time, time between accesses to successive rows, and time between accesses to successive columns, and wherein the method further comprises causing the interface, in a manner timed according to the timing parameters, to transmit at least of one the command to the device or to transfer, with the device, associated data.

16. The method of claim 12 , wherein the received information specifies a number of the memory dies in the stack configuration.

17. The method of claim 12 , wherein the method further comprises causing circuitry of the memory controller to program information into a register on the device, an access to each selected memory die then being performed by the device according to the information programmed into the register by the memory controller.

18. A memory controller for controlling a first device having memory dies in a first stack configuration and a second device having memory dies in a second stack configuration, the memory controller comprising:

at least one interface to transmit, to the first device, a first command and a first signal selecting the first device, the first command having multiple bit values, and to the second device, a second command and a second signal selecting the second device, the second command also having multiple bit values;

circuitry to format the multiple bit values of the first command so as to select a memory die of the memory dies in the first stack configuration, for a first memory access, and to format the multiple bit values of the second command so as to select a memory die of the memory dies in the second stack configuration, for a second memory access; and

circuitry to receive information from a register associated with at least one of the first device and the second device, and to responsively configure at least one circuit dependent on the received information, at least one of the first memory access and the second memory access being performed in a manner dependent on the configuration of the at least circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2025
From: RAMBUS INC.
To: SIGNAL LLP
Reel/Frame 073085/0650 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2023
From: SHAEFFER, IAN; HAMPEL, CRAIG; TSERN, ELY
To: RAMBUS INC.
Reel/Frame 064050/0325 →
Continuity (16)
Continuation 17717632 · Apr 11, 2022
Continuation 17323889 · May 18, 2021
Continuation 16842368 · Apr 7, 2020
Continuation 16692043 · Nov 22, 2019
Continuation 16214986 · Dec 10, 2018
Continuation 15832468 · Dec 5, 2017
Continuation 15389409 · Dec 22, 2016
Continuation 14801723 · Jul 16, 2015
Continuation 14015648 · Aug 30, 2013
Continuation 13149682 · May 31, 2011
Continuation 12703521 · Feb 10, 2010
Continuation 12424442 · Apr 15, 2009
Division 11697572 · Apr 6, 2007
Continuation In Part 11460899 · Jul 28, 2006
Continuation In Part 11236401 · Sep 26, 2005
Related Publication 20230410890A1 · Dec 21, 2023
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