Memory dies, stacked memories, memory devices and methods
Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.
1. A stack of memory dies comprising:
a plurality of select related connection nodes on corresponding memory dies, each being configured to receive a select signal depending on how the dies are arranged in the stack of memory dies and wherein at least one of the select related connection nodes comprises an external select connection node configured to receive a select signal; and
a plurality of identification circuits, wherein each of the identification circuits corresponds to a respective one of the memory die of the stack, wherein each of the identification circuits can be coupled to one or more of the plurality of select related connection nodes, depending on how the respective die is arranged in the stack, and wherein each of the identification circuits is configured to determine an identification of its respective memory die responsive to how, if coupled, that identification circuit is coupled to the at least one of the select related connection nodes configured to receive a select signal,
wherein the select nodes on one memory die are routed to select nodes on another memory die by routing which is separate from location of the identification circuits.
2. The stack of memory dies of claim 1 , wherein each of the identification circuits is coupled to a plurality of select related through-substrate vias in its respective memory die.
3. The stack of memory dies of claim 1 , wherein each die has a number of corresponding select related connection nodes, and wherein the number of select related connection nodes corresponding to each die equals the number of memory dies in the stack.
4. The stack of memory dies of claim 1 , wherein the number of memory dies in the stack equals four and each of the die have a respective four corresponding ones of the select related connection nodes, wherein the respective four corresponding ones of the select related connection nodes of one of the dies comprise four external select connection nodes.
5. The stack of memory dies of claim 1 , wherein the number of memory dies in the stack equals four and each of the die have at least a respective two corresponding ones of the select related connection nodes, wherein the respective two corresponding ones of the select related connection nodes of one of the dies comprises two external select connection nodes, wherein each of the die comprises at least two floating select related through-substrate vias.
6. The stack of memory dies of claim 1 , wherein the number of memory dies in the stack equals four and each of the die have at least a respective corresponding one of the select related connection nodes, wherein the respective select related connection node of one of the dies comprises a select connection node, wherein each of the die comprises at least three floating select related through-substrate vias.
7. The stack of memory dies of claim 1 , wherein a select related through-substrate via of one of the memory die in the stack is coupled to a select related through-substrate via of an adjacent one of the memory die, wherein the coupled select related through-substrate vias are not vertically aligned.
8. A memory device comprising:
an external select connection node on corresponding memory die; and
a plurality of memory dies arranged in a stack, wherein each memory die comprises a plurality of internal select related nodes and an identification circuit, each of the identification circuits comprising a plurality of detection circuits, each of the detection circuits coupled to a respective one of the plurality of internal select related nodes of the corresponding die, wherein each of the identification circuits is configured to determine an identification of its respective memory die responsive to which, if any, of the internal nodes of the respective die are coupled to the external select connection node,
wherein the select nodes on one memory die are routed to select nodes on another memory die by routing which is separate from location of the identification circuits.
9. The memory device of claim 8 , wherein the external select connect node is configured overlying the stack.
10. The memory device of claim 8 , wherein the external select connect node is configured underlying the stack.
11. The memory device of claim 8 , wherein the memory device includes a plurality of external select connect nodes.
12. The memory device of claim 11 , wherein the plurality of external select connect nodes are configured overlying the stack.
13. The memory device of claim 11 , wherein the plurality of external select connect nodes are configured underlying the stack.
14. The memory device of claim 8 , wherein the memory device comprises a plurality of external chip-select connection nodes such that the determination of the identification of its respective memory die is responsive to which, if any, of the internal nodes are coupled to one of the external chip-select connection nodes.
15. The memory device of claim 8 , wherein each detection circuit includes a current-sense circuit.
16. The memory device of claim 15 , wherein the current-sense circuit includes a current limiter to limit a sense current directed to an associated select related connection node.
17. The memory device of claim 15 , wherein the current-sense circuit includes a source node from which to generate a reference current to mirror a sense current to set the detection signal from the respective detection circuit.
18. The memory device of claim 8 , wherein each detection circuit includes a voltage detection circuit.
19. The memory device of claim 18 , wherein the voltage detection circuit includes a reset input configured to set the detection signal from the respective detection circuit on a trailing edge of a reset signal.