Memory system topologies including a memory die stack
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
1. An integrated circuit device comprising:
an interface to communicate with a first plurality of stacks of memory dies, each memory die of each stack having a respective array of memory cells; and
the interface to transmit to the first plurality of stacks
a first chip select signal to select each stack of the first plurality of stacks for the memory access, and
a memory access command that specifies the memory access, the memory access command including information to select a particular one of the memory dies within each stack of the first plurality of stacks for the memory access.
2. The integrated circuit device of claim 1 wherein the interface is to transmit a packet to the first plurality of stacks, the packet comprising the memory access command and an address, the address to identify a memory location in the particular one of the memory dies within each of the first plurality of stacks for the memory access.
3. The integrated circuit device of claim 2 wherein the information is part of the address.
4. The integrated circuit device of claim 3 wherein the information is part of a bank address field of the address.
5. The integrated circuit device of claim 1 wherein the interface is to transmit to a second plurality of stacks of memory dies a second chip select signal, to select each stack of the second plurality of stacks for the memory access.
6. The integrated circuit device of claim 1 further comprising an interface to transfer data between the integrated circuit device and the particular one of the memory dies within each of the first plurality of stacks for the memory access.
7. The integrated circuit device of claim 1 wherein the integrated circuit device is a memory controller device.
8. The integrated circuit device of claim 5 wherein the first plurality of stacks is disposed on a memory module comprising a serial presence detect (SPD) device and wherein the integrated circuit is to access the SPD device to retrieve configuration information relating to the first plurality of stacks.
9. The integrated circuit device of claim 1 wherein array respective array of memory cells is an array of dynamic random access memory (DRAM) cells and wherein the integrated circuit is a DRAM memory controller integrated circuit.
10. A integrated circuit device comprising:
an interface to communicate with at least one stack of memory dies, each memory die of the at least one stack having a respective array of memory cells;
the interface to transmit
a chip select signal to select a given stack of the at least one stack for a memory access, and
a memory access command that specifies the memory access, the memory access command including information to select
a particular die within the given stack for the memory access, and
a memory location within the array respective to the particular die for the memory access.
11. The integrated circuit device of claim 10 wherein the interface is to transmit a packet, the packet comprising the memory access command and an address, the address to identify a memory location in the respective array of the particular die for the memory access.
12. The integrated circuit device of claim 11 wherein the integrated circuit device is to transmit an address in association with the memory access command and wherein the information is part of the address.
13. The integrated circuit device of claim 10 wherein:
the given stack comprises a buffer die;
the interface is to be coupled to the buffer die; and
the buffer die is to receive the information from the interface and is to retransmit the memory access command to the particular die.
14. The integrated circuit device of claim 13 wherein the information is part of a bank address field of the address.
15. The integrated circuit device of claim 10 wherein:
the given stack has a buffer die;
the interface is to be coupled to the buffer die;
the buffer die is to generate a second chip select signal, internal to the given stack, to select the particular die; and
the buffer die is to retransmit the memory access command for the given stack to the particular die of the given stack.
16. The integrated circuit device of claim 15 wherein:
the integrated circuit device further comprises an interface to transfer data between the integrated circuit device and the buffer die; and
the buffer die is to transfer the data between a memory controller integrated circuit and the particular die of the given stack.
17. The integrated circuit device of claim 15 wherein:
the interface is a command interface;
the integrated circuit device further comprises a data interface to transfer data between the integrated circuit device and the given stack;
the given stack is to store a slice of data;
the data interface is not to transfer the slice of data between the integrated circuit device and the buffer die in association with the memory access command; and
the data interface is to transfer the slice of data between the integrated circuit device and the particular die of the given stack.
18. A method of operation of an integrated circuit device having an interface to communicate with a first plurality of stacks of memory dies, each memory die of each stack having a respective array of memory cells, the method comprising:
transmitting to the first plurality of stacks, a first chip select signal to select each stack of the first plurality of stacks for the memory access; and
transmitting to the first plurality of stacks, in association with the first chip select signal, a memory access command that specifies the memory access, the memory access command including information to select a particular one of the memory dies within each stack of the first plurality of stacks for the memory access.
19. The method of claim 18 further comprising transmitting to a second plurality of stacks of memory dies, a second chip select signal to select each stack of the second plurality of stacks for the memory access.
20. The method of claim 19 wherein the integrated circuit device is a memory controller device.