Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation
A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
1. A controller device to control the operation of an electrically erasable programmable memory chip, the controller device comprising:
a transmitter circuit to transmit a read command and a first error detection code to the memory chip;
a receiver circuit to receive read data and a second error detection code from the memory chip, the second error detection code encoded by the memory chip in connection with the read data;
a circuit, coupled to the receiver, to detect an error in the received read data based on the second error detection code; and
logic circuitry to signal an error condition in the event of the detected error, the controller device to re-receive the read data from the memory chip in the event that the logic circuitry signals the error condition;
wherein the memory chip is to detect existence of error in the read command using the first error detection code; and
wherein at least one of the first error code and the second error detection code is to be exchanged between the controller device and the memory chip using a link independent of a link used to receive the read data.
2. The controller device of claim 1 , wherein each of the first error detection code and the second error detection code is to include a cyclic code.
3. The controller device of claim 1 , further comprising logic to execute a retry remedial action, wherein, in the event of the detected error, the controller device is to perform the retry remedial action including re-transmission of a read command corresponding to the received read data.
4. The controller device of claim 3 , wherein the controller device is to generate an error correction code in association with the re-transmitted read command.
5. The controller device of claim 1 , wherein the receiver circuit comprises a first receiver to receive the read data via a data link, and a second receiver to receive the second error detection code via the link independent of a link used to receive the read data.
6. The controller device of claim 1 , further comprising logic to execute a retry remedial action, wherein in the event of the detected error, the controller device is to re-receive the read data in a manner where the read data is accompanied with blanks.
7. The controller device of claim 1 , further comprising a circuit to perform a serial-to-parallel conversion on the read data and second error detection code.
8. The controller device of claim 1 , further comprising logic to execute a retry remedial action, wherein in the event of the detected error, the controller device is to re-receive the read data from by the memory chip at a different data rate than a data rate used when the read data was first received at the receiver circuit.
9. The controller device of claim 1 , further comprising logic to execute a retry remedial action, wherein in the event of the detected error, the controller device is to re-receive the read data from the memory chip in a manner where the re-received read data has a larger voltage swing than the voltage swing than when the read data was first received at the receiver circuit.
10. The controller device of claim 1 , embodied as a dynamic random access memory (DRAM) controller.
11. A method of operation in a controller device, the method comprising:
transmitting a read command and a first error detection code to an electrically erasable programmable memory chip;
receiving read data and second error detection code from the memory chip, the second error detection code encoded by the memory chip using the read data;
detecting error in the received read data based on the second error detection code;
signaling an error condition to the memory chip in the event of the detected error; and
re-receiving the read data from the memory chip in the event that the error condition is signaled to the memory chip;
wherein the memory chip is to detect existence of error in the read command using the first error detection code; and
wherein at least one of the first error code and the second error detection code is to be exchanged between the controller device and the memory chip using a link independent of a link used to receive the read data.
12. The method of claim 11 , further comprising performing a retry remedial action in the event of the error condition, wherein the retry remedial action comprises re-receiving the read data re-transmitted by the memory chip using a larger voltage swing than the voltage swing used when first received at the receiver circuit.
13. The method of claim 11 , further comprising performing a retry remedial action in the event of the error condition, wherein the remedial retry action includes re-transmitting a read command corresponding to the read data.
14. The method of claim 13 , wherein the re-transmitting the read command includes generating an error correction code to protect the re-transmitted read command.
15. The method of claim 11 , further comprising performing a retry remedial action in the event of the error condition, wherein the retry remedial action further comprises re-receiving the read data from by the memory chip data at a different data rate than a data rate used to originally receive the read data at the receiver circuit.
16. The method of claim 11 , further comprising performing a retry remedial action in the event of the error condition, wherein the retry remedial action further comprises re-receiving the read data re-transmitted by the memory chip with blanks attached.
17. The method of claim 11 , further comprising performing a serial-to-parallel conversion on the read data and second error detection code.
18. The method of claim 11 , wherein each of the first error detection code and the second error detection code includes a cyclic code.
19. A controller device, comprising:
means for transmitting a read command and a first error detection code to an electrically erasable programmable memory chip;
means for receiving read data and a second error detection code from the memory chip, the second error detection code encoded by the memory chip using the read data;
means for detecting error in the received read data based on the second error detection code;
means for signaling an error condition to the memory chip in the event of the detected error; and
means for re-receiving the read data in the event that the error condition is signaled to the memory chip;
wherein the memory chip is to detect existence of error in the read command using the first error detection code; and
wherein at least one of the first error code and the second error detection code is to be exchanged between the controller device and the memory chip using a link independent of a link used to receive the read data.
20. The method of claim 11 , further comprising using a first receiver to receive the read data via a data link, and a second receiver to receive the second error detection code via the link independent of a link used to receive the read data.