On-die termination of address and command signals
A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal; and a third register field to store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal. The memory device also includes second and third registers to store values for selecting one of the plurality of CA ODT impedance values and one of the plurality of CS ODT impedance values for application to the first inputs and second input, respectively.
1. A memory device comprising:
a set of inputs, including first inputs to receive command/address (CA) signals, a second input to receive a chip select (CS) signal, and third inputs to receive a clock (CK) signal;
a first register comprising a plurality of register fields, wherein:
a first register field is configured to store a value for enabling application of one of a plurality of CA on-die termination (ODT) impedance values to the first inputs that receive the CA signals;
a second register field is configured to store a value for enabling application of one of a plurality of CS ODT impedance values to the second input that receives the CS signal; and
a third register field is configured to store a value for enabling application of a CK ODT impedance value to the third inputs that receive the CK signal;
a second register comprising a plurality of register fields configured to store values for selecting one of the plurality of CA ODT impedance values for application to the first inputs that receive the CA signals; and
a third register configured to store values for selecting one of the plurality of CS ODT impedance values for application to the second input that receives the CS signal.
2. The memory device of claim 1 , wherein the CA ODT impedance values are different from the CS ODT impedance values.
3. The memory device of claim 2 , further including ODT circuitry to apply a selected one of the CS ODT impedance values as a termination impedance to the second input that receives the CS signal and to apply a selected one of the CA ODT impedance values as a termination impedance to the first inputs that receive the CA signals.
4. The memory device of claim 1 , wherein the plurality of register fields in the second register include a first register field to store a first value for setting a nominal termination impedance for the first inputs that receive the CA signals, and a second register field to store a second value for setting an alternative termination impedance for the first inputs that receive the CA signals.
5. The memory device of claim 4 , wherein the plurality of register fields in the second register include a third register field to store a third value for specifying how the alternative termination impedance for the first inputs that receive the CA signals is enabled.
6. The memory device of claim 4 , further including a pin to receive a voltage level that selects one of the plurality of CA ODT impedance values for ODT to apply to the first inputs that receive the CA signals.
7. The memory device of claim 1 , further including a first pin to receive a first voltage level that selects one of the plurality of CA ODT impedance values for ODT to apply to the first inputs that receive the CA signals.
8. The memory device of claim 7 , further including ODT circuitry, and a second pin to receive a second voltage level that, in combination with the first voltage level, selects one of a first impedance value for the ODT circuitry to apply to the first inputs that receive the CA signals, a second impedance value for the ODT circuitry to apply to the first inputs that receive the CA signals, or a high impedance state for the ODT circuitry.
9. The memory device of claim 8 , further including a third pin to receive an on-die termination enable signal, wherein the ODT circuitry is disabled when the received on-die termination enable signal has a first predefined value and the ODT circuitry is enabled when the received on-die termination enable signal has a second predefined value.
10. A memory device comprising:
a set of inputs, including first inputs to receive command/address (CA) signals, a second input to receive a chip select (CS) signal, and third inputs to receive a clock (CK) signal;
a first register comprising a plurality of register fields, wherein:
a first group of register fields are configured to store values for selecting one of a plurality of CS on-die termination (ODT) impedance values for application to the second input that receives the CS signal; and
a second group of register fields are configured to store values for selecting one of a plurality of CK ODT impedance values for application to the third inputs that receive the CK signal; and
a second register comprising a plurality of register fields configured to store values for selecting one of a plurality of CA ODT impedance values for application to the first inputs that receive the CA signals.
11. The memory device of claim 10 , wherein the CA ODT impedance values, CK ODT impedance values and CS ODT impedance values are different.
12. The memory device of claim 11 , further including ODT circuitry to apply a selected one of the plurality of CS ODT impedance values as a termination impedance to the second input that receive the CS signal, a selected one of the plurality of CK ODT impedance values as a termination impedance to the third inputs that receive the CK signal, and a selected one of the plurality of CA ODT impedance values as a termination impedance to the first inputs that receive the CA signals.
13. The memory device of claim 10 , wherein the CA ODT impedance values are different from the CS ODT impedance values.
14. The memory device of claim 10 , wherein the plurality of register fields in the second register include a first register field to store a first value for setting a nominal termination impedance for the first inputs that receive the CA signals, and a second register field to store a second value for setting an alternative termination impedance for the first inputs that receive the CA signals.
15. The memory device of claim 14 , wherein the plurality of register fields in the second register include a third register field to store a third value for specifying how the alternative termination impedance for the first inputs that receive the CA signals is enabled.
16. The memory device of claim 14 , further including a pin to receive a voltage level that selects one of the plurality of CA ODT impedance values for ODT to apply to the first inputs that receive the CA signals.
17. The memory device of claim 10 , further including a first pin to receive a first voltage level that selects one of the plurality of CA ODT impedance values for ODT to apply to the first inputs that receive the CA signals.
18. The memory device of claim 17 , further including ODT circuitry, and a second pin to receive a second voltage level that, in combination with the first voltage level, selects one of a first impedance value for the ODT circuitry to apply to the first inputs that receive the CA signals, a second impedance value for the ODT circuitry to apply to the first inputs that receive the CA signals, or a high impedance state for the ODT circuitry.
19. The memory device of claim 18 , further including a third pin to receive an on-die termination enable signal, wherein the ODT circuitry is disabled when the received on-die termination enable signal has a first predefined value and the ODT circuitry is enabled when the received on-die termination enable signal has a second predefined value.
20. A method of operating a memory device, the method comprising:
receiving command/address (CA) signals, a chip select (CS) signal, and a clock (CK) signal, at a plurality of inputs;
storing values in a first register of the memory device, including
storing in a first register field of the first register, a value for enabling application of one of a plurality of CA on-die termination (ODT) impedance values to the inputs that receive the CA signals;
storing in a second register field of the first register, a value for enabling application of one of a plurality of CS ODT impedance values to the input that receives the CS signal; and
storing in a third register field of the first register, a value for enabling application of a CK ODT impedance value to the inputs that receive the CK signal;
storing in a second register of the memory device, a value for selecting a CA ODT impedance value of the plurality of CA ODT impedance values;
storing in a third register of the memory device, a value for selecting a CS ODT impedance value of the plurality of CS ODT impedance values; and
applying termination impedances to the plurality of inputs that receive the CA signals and CS signal respectively in accordance with the values stored in the second register and third register.