On-die termination of address and command signals
A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A memory controller sends register values, for storage in a plurality of registers of a respective memory device. The register values include register values that represent one or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals, and one or more register values to selectively enable application of a chip select ODT impedance to the chip select input of the respective memory device.
1. A memory device, comprising:
a plurality of inputs to receive a plurality of command/address (CA) signals;
a pin to receive a voltage level that selects one of a plurality of configurable impedance values for on-die termination (ODT) to apply to each of the plurality of inputs that receive the plurality of command/address signals;
an input to receive a chip select signal;
an input to receive a clock signal;
a register to store:
a first register value to selectively enable application of an ODT impedance to the input that receives the chip select signal; and
a second register value to selectively enable application of an ODT impedance to the input that receives the clock signal.
2. The memory device of claim 1 , further comprising on-die termination (ODT) circuitry to couple to the plurality of inputs that receive the plurality of command/address signals, wherein the register is to store a third register value that selects an impedance value for the ODT circuitry.
3. The memory device of claim 2 , wherein the pin is a first pin, the voltage level is a first voltage level, and the memory device further includes a second pin to receive a second voltage level that, in combination with the first voltage level, selects one of a first impedance value for the on-die termination, a second impedance value for the on-die termination, or a high impedance state for the ODT circuitry.
4. The memory device of claim 3 , further including a third pin to receive an on-die termination enable signal, wherein the ODT circuitry is disabled when the received on-die termination enable signal has a first predefined value and the ODT circuitry is enabled when the received on-die termination enable signal has a second predefined value.
5. The memory device of claim 4 , wherein the register is to store an override value for overriding the on-die termination enable signal.
6. The memory device of claim 2 , wherein the third register value selects one of a first termination value and a second termination value.
7. The memory device of claim 6 , wherein the first termination value corresponds to a strong termination and the second termination value corresponds to a weak termination.
8. The memory device of claim 2 , wherein the ODT circuitry is further configured to apply a termination impedance having a different impedance value to the input that receives the chip select signal than an ODT impedance applied to the plurality of inputs that receive the command/address signals.
9. The memory device of claim 1 , wherein the plurality of configurable impedance values for on-die termination includes a first impedance value corresponding to a first voltage level on the pin, and a second impedance value corresponding to a second voltage level on the pin.
10. The memory device of claim 1 , wherein the register is to store a third register value to specify an impedance value of the ODT impedance to be applied to the input that receives the clock signal.
11. The memory device of claim 1 , wherein the register is to store a fourth register value to specify an impedance value of the ODT impedance to be applied to the input that receives the chip select signal.
12. A method of operating a memory device, the method comprising:
receiving a plurality of command/address signals at a plurality of inputs;
receiving a voltage level at a first pin of the memory device, and in accordance with the voltage level received at the first pin, selecting one of a plurality of configurable impedance values for on-die termination (ODT), to apply to each of the plurality of inputs that receive the plurality of command/address signals;
storing register values in a register of the memory device;
at a first input, receiving a chip select signal wherein the register values include one or more register values to selectively enable application of an ODT impedance to the first input; and
at a second input, receiving a clock signal, wherein the register values include one or more register values to selectively enable application of an ODT impedance to the second input.
13. The method of claim 12 , including coupling on-die termination (ODT) circuitry of the memory device to the plurality of inputs that receive the plurality of command/address signals.
14. The method of claim 13 , wherein the voltage level is a first voltage level, and the method includes receiving at a second pin of the memory device a second voltage level that, in combination with the first voltage level, selects one of a first impedance value for the on-die termination, a second impedance value for the on-die termination, or a high impedance state for the ODT circuitry.
15. The method of claim 14 , further including receiving on a third pin of the memory device an on-die termination enable signal, disabling the ODT circuitry when the received on-die termination enable signal has a first predefined value, and enabling the ODT circuitry when the received on-die termination enable signal has a second predefined value.
16. The method of claim 15 , including overriding the on-die termination enable signal when the register values include a predefined override value.
17. The method of claim 13 , wherein the ODT circuitry includes a plurality of circuit elements, and the method includes controlling a setting of at least one of the plurality of circuit elements in accordance with the voltage level received at the first pin of the memory device.
18. The method of claim 13 , wherein the register values include an on-die termination enable signal, and the method includes disabling the ODT circuitry when the on-die termination enable signal has a first predefined value, and enabling the ODT circuitry when the on-die termination enable signal has a second predefined value.
19. The method of claim 13 , including applying, using the ODT circuitry, a termination impedance having a different impedance value to the input that receives the chip select signal than the ODT impedance applied to the plurality of inputs that receive the plurality of command/address signals.
20. An integrated circuit device, comprising:
a plurality of inputs to receive a plurality of command/address (CA) signals that specify a memory access for a dynamic random access memory device (DRAM);
a pin to receive a voltage level that selects one of a plurality of configurable impedance values for on-die termination (ODT), to apply to each of the plurality of inputs that receive the plurality of command/address signals;
an input to receive a chip select signal;
an input to receive a clock signal;
a register to store:
a first register value to selectively enable application of an ODT impedance to the input that receives the chip select signal; and
a second register value to selectively enable application of an ODT impedance to the input that receives the clock signal.