On-die termination of address and command signals
A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.
1. A memory device comprising:
inputs to receive command and address signals from a command and address bus;
on-die termination (ODT) circuitry to couple to the inputs;
one or more register fields that store register values to specify an impedance value, of an ODT impedance of the ODT circuitry, to be applied to each of the inputs, wherein, when applied, each input includes a corresponding ODT impedance having the impedance value;
an input to receive a chip select signal, wherein the register values include one or more register values to selectively enable application of an ODT impedance to the input that receives the chip select signal; and
an input to receive a clock signal, wherein the register values include one or more register values to selectively enable application of an ODT impedance to the input that receives the clock signal.
2. The memory device of claim 1 , further comprising a pin to receive an ODT enable signal having one of a first voltage and second voltage such that the memory device enables application of the ODT circuitry, with respect to each of the inputs that receive the command and address signals, in response to the ODT enable signal having the first voltage and disables operation of the ODT circuitry, with respect to each of the inputs that receive the command and address signals, in response to the ODT enable signal having the second voltage.
3. The memory device of claim 2 , further comprising one or more register fields that specify an override of the ODT enable signal.
4. The memory device of claim 3 , wherein a first setting of a respective register value in the one or more register fields that specifies the override enables application of the ODT impedance to each input that receives the command and address signals in response to the ODT enable signal and a second setting of the respective register value in the one or more register fields that specifies the override causes the memory device to ignore the ODT enable signal.
5. The memory device of claim 1 , wherein the memory device is one memory device in a group of memory devices, each memory device of the group having an instance of the on-die termination (ODT) circuitry and an instance of the one or more register fields, and wherein a last memory device in the group of memory devices is configured to enable operation of the ODT circuitry, and other memory devices in the group of memory devices are configured to disable the ODT circuitry.
6. The memory device of claim 1 , wherein the one or more register fields include one or more register values to specify an impedance value of the ODT impedance to be applied to the input that receives the clock signal.
7. The memory device of claim 1 , further comprising a request interface having the input to receive the clock signal and the input to receive the chip select signal, wherein the inputs to receive the command and address signals comprise a subset of inputs included on the request interface.
8. The memory device of claim 1 , wherein the one or more register fields include one or more register values to specify an impedance value of the ODT impedance to be applied to the input that receives the chip select signal.
9. The memory device of claim 1 , wherein the one or more register fields include a respective register field to store a value that determines how application, by the ODT circuitry, of the ODT impedance to the inputs that receive the command and address signals with an alternative impedance value is enabled in response to an ODT enable signal.
10. The memory device of claim 1 , wherein the ODT circuitry is further configured to apply a termination impedance having a different impedance value to the input that receives the chip select signal than the ODT impedance applied to the inputs that receive the command and address signals.
11. A method of operating a memory device, the method comprising:
receiving command and address signals at inputs;
storing register values in the memory device,
wherein the register values include a register value to specify an impedance value of an ODT impedance to be applied to each of the inputs, wherein, when applied, each input includes a corresponding ODT impedance having the impedance value;
receiving a chip select signal, wherein the register values include one or more register values to selectively enable application of an ODT impedance to the input that receives the chip select signal; and
receiving a clock signal, wherein the register values include one or more register values to selectively enable application of an ODT impedance to the input that receives the clock signal.
12. The method of claim 11 , further comprising:
receiving an ODT enable signal having one of a first voltage and second voltage;
enabling application of the ODT impedance to each of the inputs in response to the ODT enable signal having the first voltage; and
disabling application of the ODT impedance to each of the inputs, in response to the ODT enable signal having the second voltage.
13. The method of claim 11 , further comprising overriding the application of the ODT impedance to each of the inputs as enabled by the ODT enable signal, based on a respective register value stored in one or more register fields in the memory device.
14. The method of claim 13 , further comprising setting the respective register value, wherein a first setting of the respective register value enables application of the ODT impedance to the inputs in response to the ODT enable signal and a second setting of the respective register value causes the memory device to ignore the ODT enable signal.
15. The method of claim 11 , further comprising storing one or more register values to specify an impedance value of the ODT impedance to be applied to an input that receives the clock signal.
16. The method of claim 11 , further comprising storing one or more register values to specify an impedance value of the ODT impedance to be applied to an input that receives the chip select signal.
17. The method of claim 11 , further comprising applying termination impedances having different impedance values to an input that receives the chip select signal and the inputs that receive the command and address signals.
18. The method of claim 11 , wherein the impedance value is a nominal impedance value, and the method further comprises storing register values to specify both the nominal impedance value and an alternative impedance value to be applied to the inputs of the memory device that receive the command and address signals.
19. The method of claim 11 , wherein the memory device is a dynamic random access memory device.
20. A memory device comprising:
inputs to receive command and address signals from a command and address bus;
on-die termination (ODT) circuitry to couple to the inputs;
means for storing register values to specify an impedance value, of an ODT impedance of the ODT circuitry, to be applied to each of the inputs, wherein, when applied, each input includes a corresponding ODT impedance having the impedance value;
an input to receive a chip select signal, wherein the register values include one or more register values to selectively enable application of an ODT impedance to the input that receives the chip select signal; and
an input to receive a clock signal, wherein the register values include one or more register values to selectively enable application of an ODT impedance to the input that receives the clock signal.