On-die termination of address and command signals
A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.
1. A dynamic random access memory device (DRAM) comprising:
inputs to receive command/address (CA) signals;
a first one of the inputs to receive a chip select signal; and
a plurality of registers to store values that represent one or more impedance values of on-die termination (ODT) impedances to apply to respective inputs that receive the CA signals, and wherein the values include one or more register values to selectively enable application of a chip select ODT impedance to the first one of the inputs that receives the chip select signal.
2. The DRAM of claim 1 , wherein a second one of the inputs is to receive a clock signal, wherein the register values include one or more register values to selectively enable application of a clock signal ODT impedance to the second one of the inputs that receives the clock signal.
3. The DRAM of claim 2 , wherein the register values include one or more register values to specify an impedance value of the chip select ODT impedance to be applied to the first one of the inputs, which receives the chip select signal.
4. The DRAM of claim 2 , wherein the register values include one or more register values to specify an impedance value of the clock signal ODT impedance to be applied to the second one of the inputs, which receives the clock signal.
5. The DRAM of claim 1 , wherein a third one of the inputs is to receive an ODT enable signal having one of a first voltage and second voltage such that the memory device enables application of the ODT impedances, with respect to each of the inputs that receive the CA signals, in response to the ODT enable signal having the first voltage and disables operation of the ODT circuitry, with respect to each of the inputs that receive the CA signals, in response to the ODT enable signal having the second voltage.
6. The DRAM of claim 5 , wherein the values include one or more override register values that specify an override of the ODT enable signal.
7. The DRAM of claim 6 , wherein a first setting of the override register value enables application of the ODT impedances to each of the respective inputs in response to the ODT enable signal and a second setting of the override register value specifies the override causes the memory device to ignore the ODT enable signal.
8. The DRAM of claim 1 , wherein the values include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals.
9. The DRAM of claim 1 , further comprising a pin to receive an ODT enable signal, wherein the ODT impedances are applied to one or more of the inputs that receive the CA signals in according to a voltage applied to the pin.
10. The DRAM of claim 9 , wherein the values include one or more register values to override the voltage applied to the pin and selectively enable application of the ODT impedances to the respective inputs that receive the CA signals.
11. The DRAM of claim 1 , wherein an impedance value of the chip select ODT impedance is specified by the values that specify the impedance values of the ODT impedances to apply to the inputs that receive the CA signals.
12. A memory device comprising:
inputs to receive command and address information via a command and address (CA) bus;
on-die termination (ODT) impedances to selectively couple to the respective inputs that receive the command and address information;
at least one input to receive a clock signal; and
register fields to store register values to specify one or more impedance values of the ODT impedances, wherein the register values include one or more register values to selectively enable application of a clock signal ODT impedance to the at least one input of the memory device that receives the clock signal.
13. The memory device of claim 12 , further comprising an input to receive a chip select signal, wherein the register values include one or more register values to selectively enable application of a chip select ODT impedance to the input of the memory device that receives the chip select signal.
14. The memory device of claim 13 , wherein the register fields store one or more register values to specify an impedance value of the chip select signal ODT impedance to be applied to the input of the memory device that receives the chip select signal.
15. The memory device of claim 12 , wherein the value of the clock signal ODT impedance is specified by the register values that specify the one or more impedance values of the ODT impedances.
16. The memory device of claim 12 , wherein the register values include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals.
17. The memory device of claim 12 , further comprising a pin to receive an ODT enable signal, wherein the ODT impedances are applied to one or more of the inputs that receive the command and address information according to a voltage applied to the pin.
18. The memory device of claim 17 , wherein the register values include one or more register values to override the voltage applied to the pin and selectively enable application of the ODT impedances to the respective inputs that receive the command and address information.
19. A memory device comprising:
a circuit to receive command and address signals from an external command and address bus;
a first input to receive a chip select signal from an external chip select signal line;
a second input to receive at least one clock signal from an external clock signal line; and
register fields to store register values, the register values to specify one or more impedance values of on die termination (ODT) impedances to be selectively applied to respective inputs that receive the command and address signals from the external command and address bus, the register values to include one or more register values to selectively enable application of a chip select signal ODT impedance to the first input, and one or more register values to selectively enable application of a clock signal ODT impedance to the second input.
20. The memory device of claim 19 , wherein the register fields store one or more register values to specify (i) an impedance value of the chip select signal ODT impedance to be applied to the first input of the memory device, which receives the chip select signal, and (ii) one or more register values to specify an impedance value of the clock signal ODT impedance to be applied to the second input of the memory device, which receives the clock signal.