On-die termination of address and command signals
A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.
1. A method of operating a dynamic random access memory device (DRAM), comprising:
receiving, at respective inputs, command/address (CA) signals, including a chip select signal received at a first input of the respective inputs;
storing, in a plurality of registers of the memory device, values that represent one or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs that receive the CA signals, wherein the values include one or more register values to selectively enable application of a chip select ODT impedance to the first input, which receives the chip select signal; and
selectively enabling application of the chip select ODT impedance to the first input in accordance with the one or more register values to selectively enable application of the chip select ODT impedance to the first input.
2. The method of claim 1 , including
receiving a clock signal at a second input of the respective inputs, wherein the register values include one or more register values to selectively enable application of a clock signal ODT impedance to the second input; and
selectively enabling application of the clock signal ODT impedance to the second input in accordance with the one or more register values to selectively enable application of the clock signal ODT impedance to the second input.
3. The method of claim 2 , wherein the register values include one or more register values to specify an impedance value of the chip select ODT impedance to be applied to the first input, which receives the chip select signal.
4. The method of claim 2 , wherein the register values include one or more register values to specify an impedance value of the clock signal ODT impedance to be applied to the second input, which receives the clock signal.
5. The method of claim 1 , including: receiving at a third input of the respective inputs an ODT enable signal having one of a first voltage and second voltage; enabling application of the ODT impedances, with respect to each of the inputs that receive the CA signals, in response to the ODT enable signal having the first voltage; and disabling application of the ODT impedances, with respect to each of the inputs that receive the CA signals, in response to the ODT enable signal having the second voltage.
6. The method of claim 5 , wherein the values stored in the plurality of registers include an override register value that specifies an override of the ODT enable signal.
7. The method of claim 6 , wherein a first setting of the override register value enables application of the ODT impedances to each of the respective inputs in response to the ODT enable signal and a second setting of the override register value causes the memory device to ignore the ODT enable signal.
8. The method of claim 1 , wherein the values stored in the plurality of registers include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals.
9. The method of claim 1 , further comprising receiving, at a pin of the memory device, an ODT enable signal, wherein the ODT impedances are applied to one or more of the inputs that receive the CA signals in according to a voltage applied to the pin.
10. The method of claim 9 , wherein the values stored in the plurality of registers include one or more register values to override the voltage applied to the pin and selectively enable application of the ODT impedances to the respective inputs that receive the CA signals.
11. The method of claim 1 , wherein an impedance value of the chip select ODT impedance is specified by the values, stored in the plurality of registers, that represent the one or more impedance values of the ODT impedances to apply to the respective inputs that receive the CA signals.
12. A method of operating a memory device, comprising:
receiving, at respective inputs of the memory device, command and address information via a command and address (CA) bus;
selectively coupling on-die termination (ODT) impedances to the respective inputs that receive the command and address information;
receiving, at at least one clock input of the memory device, a clock signal; and
storing, in register fields of the memory device, register values to specify one or more impedance values of the ODT impedances, wherein the register values include one or more register values to selectively enable application of a clock signal ODT impedance to the at least one clock input of the memory device.
13. The method of claim 12 , further comprising receiving, at an input of the memory device, a chip select signal, wherein the register values include one or more register values to selectively enable application of a chip select ODT impedance to the input of the memory device that receives the chip select signal.
14. The method of claim 13 , including storing, in the register fields, one or more register values to specify an impedance value of the chip select signal ODT impedance to be applied to the input of the memory device that receives the chip select signal.
15. The method of claim 12 , wherein a value of the clock signal ODT impedance is specified by the register values that specify the one or more impedance values of the ODT impedances.
16. The method of claim 12 , wherein the register values include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals.
17. The method of claim 12 , further comprising receiving at a pin of the memory device an ODT enable signal, wherein the ODT impedances are applied to one or more of the respective inputs that receive the command and address information according to a voltage applied to the pin.
18. The method of claim 17 , wherein the register values include one or more register values to override the voltage applied to the pin and selectively enable application of the ODT impedances to the respective inputs that receive the command and address information.
19. A method of operating a memory device, comprising:
receiving command and address signals from an external command and address bus;
receiving, at a first input of the memory device, a chip select signal from an external chip select signal line;
receiving, at a second input of the memory device, at least one clock signal from an external clock signal line;
storing, in register fields of the memory device, register values, the register values to specify one or more impedance values of on die termination (ODT) impedances to be selectively applied to respective inputs of the memory device that receive the command and address signals from the external command and address bus, the register values to include one or more register values to selectively enable application of a chip select signal ODT impedance to the first input, and one or more register values to selectively enable application of a clock signal ODT impedance to the second input; and
in accordance with the stored register values, selectively enabling application of a chip select signal ODT impedance to the first input, selectively enabling application of a clock signal ODT impedance to the second input, and selectively applying ODT impedances to the respective inputs of the memory device that receive the command and address signals from the external command and address bus.
20. The method of claim 19 , wherein the register fields store one or more register values to specify (i) an impedance value of the chip select signal ODT impedance to be applied to the first input of the memory device, which receives the chip select signal, and (ii) one or more register values to specify an impedance value of the clock signal ODT impedance to be applied to the second input of the memory device, which receives the clock signal.