MULTI-DIE MEMORY DEVICE
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
1 . (canceled)
2 . A logic integrated circuit (IC) base die for a three-dimensional memory device, comprising:
an engagement surface to mount multiple memory die that are configured as a memory stack, the multiple memory die comprising multiple independent memory interfaces;
a primary interface to communicate with memory control circuitry; and
multiple independent secondary interfaces, each of the multiple independent secondary interfaces configured to couple to a corresponding one of the multiple independent memory interfaces of the multiple memory die in a dedicated manner.
3 . The logic IC base die of claim 2 , wherein:
the primary interface comprises multiple serial signaling input/output (I/O) circuits to transfer serialized signals between the memory control circuitry and the logic IC base die.
4 . The logic IC base die of claim 2 , wherein:
the multiple independent secondary interfaces are configured as dynamic random access memory (DRAM) interfaces to couple to the multiple memory die, the multiple memory die realized as multiple DRAM die.
5 . The logic IC base die of claim 2 , wherein:
the logic IC base die is fabricated using a first process that is different than a second process used to fabricate the multiple memory die.
6 . The logic IC base die of claim 2 , wherein:
the multiple independent secondary interfaces comprise configurable width interfaces that operate at a selectable first width or a selectable second width that is different than the selectable first width.
7 . The logic IC base die of claim 6 , wherein:
a selection between the selectable first width and the selectable second width is based on a mode value.
8 . The logic IC base die of claim 7 , wherein:
the mode value is retrieved from storage.
9 . A base layer for a three-dimensional memory device, comprising:
an active substrate comprising
an engagement surface to mount multiple dynamic random access memory (DRAM) die that are configured as a memory stack, the multiple DRAM die comprising multiple independent DRAM memory interfaces;
a primary interface for communicating with DRAM memory control circuitry; and
multiple independent secondary interfaces, each of the multiple independent secondary interfaces configured to couple to a corresponding one of the multiple independent DRAM memory interfaces of the multiple DRAM die in a dedicated manner.
10 . The base layer of claim 9 , wherein:
the primary interface comprises multiple serial signaling input/output (I/O) circuits to transfer serialized signals between the DRAM memory control circuitry and the base layer.
11 . The base layer of claim 9 , wherein:
the multiple independent secondary interfaces are configured as dynamic random access memory (DRAM) interfaces to couple to corresponding ones of the multiple independent DRAM memory interfaces of the multiple DRAM die.
12 . The base layer of claim 9 , wherein:
the active substrate is fabricated using a logic process that is different than a DRAM process used to fabricate the multiple DRAM memory die.
13 . The base layer of claim 9 , wherein:
the multiple independent secondary interfaces comprise configurable width interfaces that operate at a selectable first width or a selectable second width that is different than the selectable first width.
14 . The base layer of claim 13 , wherein:
a selection between the selectable first width and the selectable second width is based on a mode value.
15 . The base layer of claim 14 , wherein:
the mode value is retrieved from storage.
16 . A method of operation in a logic integrated circuit (IC) base die of a three-dimensional memory device, the method comprising:
communicating with a memory controller via a primary interface of the logic IC base die, the logic IC base die including multiple independent secondary interfaces;
communicating with a memory stack of multiple memory die via multiple independent secondary interfaces of the logic IC base die; and
performing data transfers between the logic IC base die and the multiple memory die, the data transfers performed in a dedicated manner between at least one independent memory interface of each of the multiple memory die and a corresponding one of the multiple independent secondary interfaces of the logic IC base die.
17 . The method according to claim 16 , wherein:
the communicating with the memory controller comprises transferring serialized signals between the primary interface and the memory controller using multiple serial signaling input/output (I/O) circuits.
18 . The method according to claim 17 , wherein:
the performing data transfers is carried out in accordance with a dynamic random access memory (DRAM) signaling protocol.
19 . The method of claim 16 , further comprising:
operating the multiple independent secondary interfaces at a selectable first width or a selectable second width that is different than the selectable first width.
20 . The method of claim 19 , further comprising:
selecting between the selectable first width and the selectable second width based on a mode value.
21 . The method of claim 20 , further comprising:
retrieving the mode value from storage.