Electrically erasable programmable memory device that generates error-detection information
A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
1. A solid state memory device comprising:
an input to receive a clock signal;
a memory core;
a link interface to receive write data bits in parallel, on rising and falling edges of the clock signal, and first error-detection information from a controller, the first error-detection information encoded by the controller in connection with the write data bits;
a circuit, coupled to the link interface, to generate second error-detection information corresponding to the received write data bits;
circuitry to determine an error event based on the first error-detection information and the second error-detection information and signal an error condition if the error event is detected; and
a buffer circuit to hold the write data bits in the event that the logic circuitry signals the error condition, wherein a write operation of the write data bits to the memory core is disabled if the error event is detected.
2. The memory device of claim 1 , wherein the first error-detection information received from the controller is to include a first cyclic redundancy check (CRC) code, and the second error-detection information is to include a second CRC code.
3. The memory device of claim 1 , wherein the memory device signals the error condition to the controller for the controller to perform a remedial action, wherein the remedial action is to include re-receiving the write data bits along with command information corresponding to the write data bits from the controller.
4. The memory device of claim 3 , wherein the re-received command information is to have error protection provided by an error correction code.
5. The memory device of claim 1 wherein the link interface comprises a first receiver to receive the write data bits via a data link, and a second receiver to receive the first error-detection information via an error code link.
6. The memory device of claim 1 , wherein the second receiver receives the first error detection information after a delay time expires relative to when the first receiver receives the write data bits.
7. The memory device of claim 1 , wherein the solid state memory device is implemented on a chip.
8. The memory device of claim 7 , further comprising:
first flip-flop circuitry coupled to the first receiver, to synchronize reception of the write data bits to the clock signal; and
second flip-flop circuitry coupled to the second receiver, to synchronize reception of the first error-detection information to the clock signal.
9. The memory device of claim 1 wherein circuitry to determine the error event detects the error based on a comparison between the first error-detection information and the second error-detection information.
10. A method of operation in a solid state memory device, the method comprising:
receiving a write data bits in parallel, on rising and falling edges of a clock signal, and first error-detection information from a controller, the first error-detection information encoded by the controller using the write data bits;
generating second error-detection information corresponding to the received write data bits;
comparing the first error-detection information with the second error-detection information;
signaling an error condition to the controller if comparing the first error-detection information with the second error-detection information signals an error condition; and
performing a remedial action in the event of the error condition, the remedial action including disabling a write operation of the write data bits in the event of the error condition.
11. The method of claim 10 , wherein the remedial action comprises re-receiving the write data bits.
12. The method of claim 10 , wherein the first error-detection information received from the controller is to include a first cyclic redundancy check (CRC) code, and the second error-detection information is to include a second CRC code.
13. The method of claim 10 , wherein the remedial action is to include re-receiving command information corresponding to the write data bits.
14. The method of claim 13 , wherein the re-receiving the command information includes receiving an error correction code to protect the command information.
15. The method of claim 10 wherein receiving the write data bits and first error-detection information comprises: receiving the write data bits via a data link; and receiving the first error-detection information via an error code link.
16. The method of claim 15 , wherein receiving the write data bits and receiving the first error-detection information further comprises receiving the first error-detection information after a latency period transpires relative to receiving the write data bits.
17. The method of claim 10 further comprising performing a serial-to-parallel conversion on the write data bits and first error-detection information.
18. The method of claim 17 further comprising:
synchronizing reception of the write data bits; and
synchronizing reception of the first error-detection information.
19. The method of claim 18 wherein:
synchronizing reception of the write data bits comprises synchronizing reception of the write data bits to the clock signal; and
synchronizing reception of the first error-detection information comprises synchronizing reception of the first error-detection information to the clock signal.
20. A solid state memory device comprising:
means for receiving a write data bits in parallel, on rising and falling edges of the a clock signal, and first error-detection information from a controller, the first error-detection information encoded by the controller in connection with the write data bits;
means for generating second error-detection information corresponding to the received write data bits; and
means for comparing the first error-detection information with the second error-detection information and signal an error condition based on the first error-detection information and the second error-detection information, the memory device to perform a remedial action in the event of the error condition, the remedial action including re-receiving the write data bits, and disabling a write operation of the write data bits in the event of the error condition.