Unidirectional error code transfer for both read and write data transmitted via bidirectional data link
A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
1. A memory device integrated circuit, comprising:
a bidirectional link interface operable to transmit read data to a memory controller and to receive write data from the memory controller;
encoder logic operable to compute a memory-device-version of error-detection information for each of the write data and the read data;
a unidirectional link interface operable to transmit the memory-device-version of error-detection information to the memory controller for each of the write data and the read data; and
error detection logic to disable a write operation by the memory device integrated circuit when a comparison of first write-mask error-detection information received from the memory controller with second write-mask error-detection information generated within the memory device integrated circuit indicates that an error has occurred.
2. The memory device integrated circuit of claim 1 , further comprising:
a sideband link interface operable to receive the first write-mask error-detection information from the memory controller.
3. The memory device integrated circuit of claim 2 , wherein the sideband link interface is operable to receive the first write-mask error-detection information at a lower data rate than a data rate at which the write data is received from the memory controller via the bidirectional link.
4. The memory device integrated circuit of claim 1 , further comprising:
a request link interface operable to receive from the memory controller read and write commands and the first write-mask error-detection information, wherein the first write-mask error-detection information is conveyed to the memory device integrated circuit using in-band signaling.
5. The memory device integrated circuit of claim 1 , further comprising:
an encoder operable to receive and encode write mask information, the encoder having an output, coupled to an input of the error detection logic, to provide the second write-mask error-detection information to the error detection logic.
6. The memory device integrated circuit of claim 5 , further comprising:
circuitry to synchronize the second write-mask error-detection information output by the encoder with the first write-mask error-detection information received from the memory controller.
7. The memory device integrated circuit of claim 1 , wherein the error detection logic is operable to allow the write operation by the memory device integrated circuit to proceed when the error detection logic does not detect an error.
8. The memory device integrated circuit of claim 1 , wherein the memory device integrated circuit is operable to transmit retry instructions to the memory controller when the comparison of the first write-mask error-detection information received from the memory controller with the second write-mask error-detection information generated within the memory device integrated circuit indicates that an error has occurred.
9. The memory device integrated circuit of claim 8 , wherein the memory device integrated circuit is operable to receive write mask information in conjunction with the write data, and the retry request comprises a request that the memory controller retransmit the write mask information.
10. The memory device integrated circuit of claim 8 , wherein the memory device integrated circuit is operable to receive write mask information in conjunction with the write data, and the retry request comprises a request that the memory controller retransmit the write mask information and the write data.
11. A method of operating a memory device integrated circuit, comprising:
transmitting read data to a memory controller and receiving write data from the memory controller via a bidirectional link interface of the memory device integrated circuit;
generating a memory-device-version of error-detection information for each of the write data and the read data;
transmitting, via a unidirectional link interface, the memory-device-version of error-detection information to the memory controller for each of the write data and the read data; and
disabling a write operation by the memory device integrated circuit when a comparison of first write-mask error-detection information received from the memory controller with second write-mask error-detection information generated within the memory device integrated circuit indicates that an error has occurred.
12. The method of claim 11 , further comprising receiving the first write-mask error-detection information from the memory controller via a sideband link interface.
13. The method of claim 12 , further comprising receiving the first write-mask error-detection information at a lower data rate than a data rate at which the write data is received from the memory controller via the bidirectional link.
14. The method of claim 11 , further comprising receiving from the memory controller, via a request link interface, read and write commands and the first write-mask error-detection information, wherein the first write-mask error-detection information is conveyed to the memory device integrated circuit using in-band signaling.
15. The method of claim 11 , further comprising receiving and encoding write mask information, the encoder having an output, coupled to an input of the error detection logic, to provide the second write-mask error-detection information to the error detection logic.
16. The method of claim 11 , further comprising synchronizing the second write-mask error-detection information output by the encoder with the first write-mask error-detection information received from the memory controller.
17. The method of claim 11 , further comprising allowing the write operation by the memory device integrated circuit to proceed when the comparison does not detect an error.
18. The method of claim 11 , further comprising transmitting retry instructions to the memory controller when the comparison of the first write-mask error-detection information received from the memory controller with the second write-mask error-detection information generated within the memory device integrated circuit indicates that an error has occurred.
19. The method of claim 18 , further comprising receiving write mask information in conjunction with the write data, and the retry request comprises a request that the memory controller retransmit the write mask information.
20. The method of claim 18 , further comprising receiving write mask information in conjunction with the write data, and the retry request comprises a request that the memory controller retransmit the write mask information and the write data.