MEMORY CONTROLLER WITH ERROR DETECTION AND RETRY MODES OF OPERATION

1 . (canceled)

2 . A memory integrated circuit comprising:

at least one receiver coupled to a contact, each contact to be coupled to a corresponding conductive signaling link, to receive a write command from a memory controller, according to a first value of a transmission parameter, and to receive a first error detection code, wherein the transmission parameter comprises one of a voltage, current, timing, a data rate, or a number of write data symbols per clock cycle edge;

error detection logic operable to:

calculate a second error detection code in response to receipt of the write command;

detect a mismatch between the first error detection code and the second error detection code; and

identify existence of an error from the mismatch; and

a transmitter coupled to a contact, to transmit to the memory controller, via a conductive signaling link, a signal representing the error;

wherein, in response to receiving the signal, the memory controller is to retransmit, to the memory integrated circuit, at least one of the write command or associated write data, the retransmission by the memory controller using a second value of the transmission parameter; and

wherein the receiver comprises circuitry operable to receive, from the memory controller, and according to the second value of the transmission parameter, the retransmitted at least one of the write command or associated write data.

3 . The memory integrated circuit of claim 2 , wherein each error detection code is a cyclic code.

4 . The memory integrated circuit of claim 3 , wherein the error can include a write data error, and wherein the retransmitted at least one comprises associated write data.

5 . The memory integrated circuit of claim 3 , wherein the retransmitted at least one comprises the write command, and wherein the circuitry is further operable to receive, from the memory controller, an error correction code corresponding to the retransmitted write command.

6 . The memory integrated circuit of claim 2 , wherein the at least one receiver comprises a first receiver, operable to receive write data from a first conductive signaling link, and a second receiver, operable to receive the first error detection code from a second conductive signaling link.

7 . The memory integrated circuit of claim 2 , wherein a first contact of the memory integrated circuit is to carry write data from the memory controller, and wherein a second contact of the memory integrated circuit is to carry the signal.

8 . The memory integrated circuit of claim 2 , further comprising a buffer to store write data for a period of time sufficient to permit completion of a retry retransmission action, from the memory controller, once the error detection logic identifies the error from the mismatch.

9 . The memory integrated circuit of claim 2 , wherein the error can include a write command error, and wherein the memory integrated circuit is to store write data, in a memory array of the memory integrated circuit, notwithstanding that the error detection logic identifies the existence of the error.

10 . The memory integrated circuit of claim 2 , embodied as a dynamic random access memory (DRAM) integrated circuit.

11 . The memory integrated circuit of claim 2 wherein the receiver comprises circuitry operable to receive data from the memory controller at a per-signaling link rate of one data symbol per clock cycle edge of a receiver sampling clock.

12 . A memory system comprising:

one or more memory integrated circuits; and

a memory controller to issue write commands to the one or more memory integrated circuits;

wherein a given one of the one or more memory integrated circuits comprises circuitry to:

receive, from the memory controller, for one of the write commands which seeks to access the given one of the memory integrated circuits, corresponding write data and a corresponding error detection code; and

determine whether there is an error in the one of the write commands, as received by the given one of the memory integrated circuits;

responsive to determination that there is an error in the one of the write commands, as received by the given one of the memory integrated circuits, prevent a write operation corresponding to the write command from being completed, and also transfer information, to the memory controller, representing the determination that there is an error in the one of the write commands, as received by the given one of the memory integrated circuits;

calculate, from the corresponding write data, as received by the given one of the memory integrated circuits, write data error information; and

responsive to determination that there no error in the one of the write commands, access a storage array of the given one of the memory integrated circuits to store information, dependent on the corresponding write data, in the storage array.

13 . The memory system of claim 12 wherein:

for the one of the write commands, the corresponding error detection code is dependent on the corresponding write data, as well a memory address designated by the one of the write commands;

the circuitry is further to determine whether there is an error in the corresponding write data, as received by the given one of the memory integrated circuits; and

responsive to the determination that there is an error in the corresponding write data, as received by the given one of the memory integrated circuits, the circuitry is to correct the corresponding write data, such that the information stored in the storage array comprises an error-corrected version of the corresponding write data.

14 . The memory system of claim 13 wherein the error detection code comprises a cyclic redundancy code (CRC), and wherein the circuitry is to correct the corresponding write data using the CRC.

15 . The memory system of claim 12 wherein:

the corresponding error detection code is dependent on the corresponding write data, as well a memory address designated by the corresponding one of the write commands; and

the circuitry is further to transfer the error information, to the memory controller.

16 . The memory system of claim 15 wherein the memory controller comprises circuitry to re-issue the one of the write commands, to the given one of the memory integrated circuits, in response to a determination based on the error information that the write data has an error.

17 . The memory system of claim 15 wherein the circuitry to transfer the error information to the memory controller is to do so in a manner that is not solicited by a request from the memory controller.

18 . The memory system of claim 15 wherein the circuitry to transfer the error information to the memory controller is to do so using a link which is not used for exchange, with the memory controller, of write data or read data.

19 . The memory system of claim 12 wherein the circuitry is to transfer, to the memory controller, the information representing the determination that there is an error, in the one of the write commands, in a manner that is not solicited by a request from the memory controller.

20 . The memory system of claim 12 wherein the error detection code comprises parity information.

21 . The memory system of claim 12 wherein the memory controller comprises a serializer, wherein the circuitry of the given one of the memory integrated circuits comprises a deserializer, and wherein the circuitry of the given one of the memory integrated circuits is to deserialize the one of the write commands, using the deserializer, to generate deserialized information, and is to determine whether there is an error in the one of the write commands using the deserialized information.