Memory error detection
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
1. A dynamic random access memory (DRAM) integrated circuit, comprising:
circuitry to receive a write command and an associated address, from a memory controller;
circuitry to generate a first error detection code dependent on the associated address, the first error detection code to be used to determine whether the associated address as received by the DRAM contains an error;
circuitry to receive from the memory controller, after a delay time with respect to the write command, associated write data to be written into a memory array of the DRAM integrated circuit;
circuitry to generate, for the associated write data, a second error detection code, the second error detection code to be used to determine whether the associated write data as received by the DRAM contains an error; and
circuitry to transmit to the memory controller information to permit the DRAM integrated circuit to detect error in the associated address separately from error in the associated write data.
2. The DRAM integrated circuit of claim 1 , wherein the first error detection code comprises a cyclic-redundancy check (CRC) code, and wherein the circuitry to calculate the first error detection code comprises a CRC generator, the CRC generator to generate the CRC code.
3. The DRAM integrated circuit of claim 2 , wherein the information comprises the CRC code, and wherein the memory controller is to withhold transmission of the associated write data in response to a memory-controller-determination that the CRC code does not match error information computed by the memory controller.
4. The DRAM integrated circuit of claim 2 , wherein the write command is a first write command, wherein the circuitry to receive the associated write data from the memory controller is to receive sets of write data from the memory controller, the sets of data being associated with respective write commands, the sets of write data including the associated write data and the respective write commands including the first write command, wherein the DRAM integrated circuit is to write the sets of write data to respective addresses, including the associated address, and wherein the DRAM integrated circuit is to generate the second error detection code dependent on the sets of data.
5. The DRAM integrated circuit of claim 1 , wherein the delay time is greater than or equal to a time to calculate, using the first error detection code, whether the associated address as received by the DRAM contains an error.
6. The DRAM integrated circuit of claim 1 , wherein the memory controller, in response to detected error in associated address, is to retry a sequence of commands, and wherein the DRAM integrated circuit is to receive the sequence of commands from the memory controller.
7. The DRAM integrated circuit of claim 6 , wherein the sequence of commands comprises one or more commands which follow the write command in a command pipeline.
8. The DRAM integrated circuit of claim 6 , wherein the memory controller is to use the information from the DRAM to detect error in the associated write data separately from error in the associated address, wherein the memory controller is not to retry the sequence of commands and the DRAM integrated circuit is not to receive the sequence of commands from the memory controller in the event of detected error in the associated write data but not in the associated address.
9. The DRAM integrated circuit of claim 1 , wherein the circuitry to receive the write command is to receive the associated address at a first transmission frequency, and wherein the circuitry to receive the associated write data is to receive the associated write data at a second transmission frequency, the second transmission frequency being at least twice the first transmission frequency.
10. The DRAM integrated circuit of claim 1 , wherein the circuitry to receive the write command is to use a first signaling path, wherein the circuitry to receive the associated write data is to use a second signaling path, and wherein the circuitry to transmit the information to the memory controller is to use a third signaling path, each of the first signaling path, the second signaling path and the third signaling path being mutually-exclusive to one another.
11. The DRAM integrated circuit of claim 1 , wherein the delay time is greater than a time for the DRAM integrated circuit to generate the first error detection code and for the memory controller to receive transmission of the information from the DRAM integrated circuit.
12. A method of operating a dynamic random access memory (DRAM) integrated circuit, the memory comprising, with circuitry of the DRAM integrated circuit:
receiving a write command and an associated address, from a memory controller;
generating a first error detection code dependent on the associated address, the first error detection code to be used to determine whether the associated address as received by the DRAM contains an error;
receiving from the memory controller, after a delay time with respect to the write command, associated write data, the associated write data to be written into a memory array of the DRAM integrated circuit;
generating, for the associated write data, a second error detection code, the second error detection code to be used to determine whether the associated write data as received by the DRAM contains an error; and
transmitting to the memory controller information to permit the DRAM integrated circuit to detect error in the associated address separately from error in the associated write data.
13. The method of claim 12 , wherein the information comprises a CRC code, and wherein the memory controller is to withhold transmission of the associated write data in response to a memory-controller-determination that the CRC code does not match error information computed by the memory controller.
14. The method of claim 12 , wherein the write command is a first write command, wherein the method further comprises receiving sets of write data from the memory controller, the sets of data being associated with respective write commands, the sets of write data including the associated write data and the respective write commands including the first write command, and wherein the method further comprises writing the sets of write data to be written to respective addresses, including the associated address, and generating the second error detection code dependent on the sets of data.
15. The method of claim 12 , wherein the delay time is greater than or equal to a time to calculate, using the first error detection code, whether the write command as received by the DRAM contains an error.
16. The method of claim 12 , wherein the memory controller, in response to detected error in associated address, is to retry a sequence of commands in the event that error in an associated address is detected using the first error detection code, and wherein the method further comprises receiving the sequence of commands from the memory controller.
17. The method of claim 16 , wherein the sequence of commands comprises one or more commands in a command pipeline which follow the write command.
18. The method of claim 12 , wherein the method comprises receiving the write command using a first signaling path, receiving the associated write data using a second signaling path, and transmitting the information to the memory controller using a third signaling path, each of the first signaling path, the second signaling path and the third signaling path being mutually-exclusive to one another.
19. The method of claim 12 , wherein the delay time is greater than a time for the DRAM integrated circuit to generate the first error detection code and to transmit the information to the memory controller.
20. A dynamic random access memory (DRAM) integrated circuit, comprising:
means for receiving a write command and an associated address, from a memory controller;
means for generating a first error detection code dependent on the associated address, the first error detection code to be used to determine whether the associated address as received by the DRAM contains an error;
means for receiving from the memory controller, after a delay time with respect to the write command, associated write data to be written into a memory array of the DRAM integrated circuit;
means for generating, for the associated write data, a second error detection code, the second error detection code to be used to determine whether the associated write data as received by the DRAM contains an error; and
means for transmitting to the memory controller information to permit the DRAM integrated circuit to detect error in the associated address separately from error in the associated write data.