IP Library › Granted Patent US 12,253,903
Granted Patent B2
US 12,253,903 · App. 18/140,133 · Granted Mar 18, 2025

Remedial action indication

Inventors: Yuanlong Wang (San Jose, CA); Frederick A. Ware (Los Altos Hills, CA)
Assignee: Rambus Inc.
G06F11/0727G06F3/0619G06F3/064G06F3/0679G06F11/073G06F11/0751G06F11/076G06F11/0793G06F11/10G06F11/1004G06F11/1008G06F11/1068G06F11/1402G06F13/4286H03M13/09H03M13/29H03M13/2906H03M13/611H04L1/0061H04L1/08H04L1/1867G06F11/1044H04L1/0003H04L1/0008H04L2001/0093
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Quick Facts
Patent No.
US 12,253,903
App. No.
18/140,133
Granted
Mar 18, 2025
Kind
B2
Abstract

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Claims (32)

1. A solid state memory device, comprising:

a link interface configurable in a first configuration and a second configuration, the first configuration to be for bidirectional communication with a controller via the link interface, the second configuration to be for unidirectional communication with the controller via the link interface, wherein the link interface includes:

receiver circuitry to receive command information, command error detection information associated with the command information, and remedial action instructions from the controller; and

circuitry to communicate a group of data bits with the controller based on the command information, the group of data bits to be time multiplexed with error-detection information; and,

circuitry to, based on the remedial action instructions, perform a remedial action.

2. The solid state memory device of claim 1 , wherein the remedial action includes a retry remedial action.

3. The solid state memory device of claim 2 , wherein the retry remedial action includes re-receiving the group of data bits and the error-detection information.

4. The solid state memory device of claim 2 , wherein the retry remedial action includes re-transmitting the group of data bits.

5. The solid state memory device of claim 2 , wherein the remedial action includes switching the link interface from the first configuration to the second configuration.

6. The solid state memory device of claim 1 , wherein the error-detection information is to include a cyclic redundancy check (CRC) code.

7. The solid state memory device of claim 2 , wherein the retry remedial action includes re-transmitting the group of data bits and re-receiving the error-detection information.

8. A method, comprising:

configuring a link interface in a first configuration and a second configuration, the first configuration to be for bidirectional communication with a controller via the link interface, the second configuration to be for unidirectional communication with the controller via the link interface, wherein the link interface includes:

in one of the first configuration and the second configuration, receiving command information, command error detection information associated with the command information, and remedial action instructions from the controller;

communicating a group of data bits with the controller based on the command information, the group of data bits being time multiplexed with data error-detection information; and,

based at least in part on the remedial action instructions, performing a remedial action.

9. The method of claim 8 , wherein the remedial action includes a retry remedial action.

10. The method of claim 9 , wherein the retry remedial action includes re-receiving the group of data bits and the error-detection information.

11. The method of claim 9 , wherein the retry remedial action includes re-transmitting the group of data bits.

12. The method of claim 9 , wherein the remedial action includes switching the link interface from the first configuration to the second configuration.

13. The method of claim 8 , wherein the error-detection information is to include a cyclic redundancy check (CRC) code.

14. The method of claim 9 , wherein the retry remedial action includes re-transmitting the group of data bits and re-receiving the error-detection information.

15. An integrated circuit, comprising:

a bi-modal link interface configurable in a first configuration to be for bidirectional operation and in a second configuration to be for unidirectional communication, the bi-modal link interface including:

receiver circuitry to receive, from a controller, command information, command error detection information associated with the command information, and a remedial action indicator; and

circuitry to communicate, with the controller, a group of data bits based on the command information, the group of data bits being time multiplexed with read data error-detection information;

remedial action circuitry to, based on the remedial action indicator, perform a remedial action.

16. The integrated circuit of claim 15 , wherein the remedial action includes a retry remedial action.

17. The integrated circuit of claim 16 , wherein the retry remedial action includes re-receiving the group of data bits and the error-detection information.

18. The integrated circuit of claim 16 , wherein the retry remedial action includes re-transmitting the group of data bits.

19. The integrated circuit of claim 16 , wherein the remedial action includes switching the link interface from the first configuration to the second configuration.

20. The integrated circuit of claim 15 , wherein the error-detection information is to include a cyclic redundancy check (CRC) code.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2025
From: RAMBUS INC.
To: SIGNAL LLP
Reel/Frame 073085/0650 →
Continuity (15)
Continuation 17728621 · Apr 25, 2022
Continuation 17068515 · Oct 12, 2020
Continuation 16282346 · Feb 22, 2019
Continuation 16022791 · Jun 29, 2018
Continuation 15855385 · Dec 27, 2017
Continuation 15341959 · Nov 2, 2016
Continuation 14823826 · Aug 11, 2015
Continuation 14806011 · Jul 22, 2015
Continuation 14175955 · Feb 7, 2014
Continuation 13752324 · Jan 28, 2013
Continuation 13398768 · Feb 16, 2012
Continuation 13013779 · Jan 25, 2011
Continuation 12479684 · Jun 5, 2009
Division 11330524 · Jan 11, 2006
Related Publication 20240184655A1 · Jun 6, 2024
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