Controller that receives a cyclic redundancy check (CRC) code for both read and write data transmitted via bidirectional data link
A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
1. A controller device to control the operation of a solid state memory device, the controller device comprising:
a link interface configurable in a first configuration and a second configuration, the first configuration to be for bidirectional communication via the link interface, the second configuration to be for unidirectional communication via the link interface, wherein the link interface includes:
transmitter circuitry to transmit command information, and command error detection information associated with the command information, to the solid state memory device; and
receiver circuitry to receive a group of read data bits output by the solid state memory device in connection with the command information, the group of read data bits being time multiplexed with read data error-detection information; and,
circuitry to determine an error condition based on the group of read data bits and the read data error-detection information, the controller device to perform a remedial action in the event that the circuitry determines the error condition.
2. The controller device of claim 1 , wherein the circuitry to determine the error condition is to generate an error code from the group of read data bits and compare the error code to the read data error-detection information to determine that the error condition exists.
3. The controller device of claim 1 , wherein the circuitry to determine the error condition is to generate an error code from the group of read data bits and compare the error code to read data error-detection information to determine that the error condition does not exist.
4. The controller device of claim 1 , wherein in the event that the circuitry determines the error condition, the link interface switches between the first configuration and the second configuration.
5. The controller device of claim 4 , wherein in the event that the circuitry determines the error condition, the link interface switches from the first configuration to the second configuration.
6. The controller device of claim 1 , wherein the read data error-detection information is to include a cyclic redundancy check (CRC) code.
7. The controller device of claim 1 , wherein the remedial action is to include re-transmitting command information, and command error detection information associated with the command information, to the solid state memory device.
8. A method, comprising:
configuring a link interface in a first configuration and a second configuration, the first configuration to be for bidirectional communication via the link interface, the second configuration to be for unidirectional communication via the link interface, wherein the link interface includes:
in one of the first configuration and the second configuration, transmitting command information, and command error detection information associated with the command information, to a solid state memory device;
receiving a group of read data bits output by the solid state memory device in connection with the command information, the group of read data bits being time multiplexed with read data error-detection information; and,
determining whether an error condition exists based on the group of read data bits and the read data error-detection information
based at least in part on determining the error condition exists, performing a remedial action.
9. The method of claim 8 , wherein determining whether the error condition exists includes generating an error code from the group of read data bits and comparing the error code to the read data error-detection information to determine that the error condition exists.
10. The method of claim 8 , wherein determining whether the error condition exists includes generating an error code from the group of read data bits and comparing the error code to the read data error-detection information to determine that the error condition does not exist.
11. The method of claim 8 , wherein in the event that the error condition is determined to exist, the link interface switches between the first configuration and the second configuration.
12. The method of claim 11 , wherein in the event that the error condition is determined to exist, the link interface switches from the first configuration to the second configuration.
13. The method of claim 8 , wherein the read data error-detection information includes a cyclic redundancy check (CRC) code.
14. The method of claim 8 , wherein the remedial action includes re-transmitting command information, and command error detection information associated with the command information, to the solid state memory device.
15. An integrated circuit, comprising:
a bi-modal link interface configurable in a first configuration to be for bidirectional operation and in a second configuration to be for unidirectional communication, the bi-modal link interface including:
transmitter circuitry to transmit command information, and command error detection information associated with the command information, to the solid state memory device; and
receiver circuitry to receive a group of read data bits output by the solid state memory device in connection with the command information, the group of read data bits being time multiplexed with read data error-detection information;
error checking circuitry to, based on the group of read data bits and the read data error-detection information determine a one of whether an error condition exists and whether the error condition does not exist; and,
remedial action circuitry to, in the event that the error checking circuitry determines the error condition exists, perform a remedial action.
16. The integrated circuit of claim 15 , wherein the error checking circuitry is to generate an error code from the group of read data bits and compare the error code to the read data error-detection information determine the one of whether an error condition exists and whether the error condition does not exist.
17. The controller device of claim 15 , wherein the error checking circuitry is to generate an error code from the group of read data bits and compare the error code to read data error-detection information to determine that the error condition exists.
18. The controller device of claim 17 , wherein in the event that the error checking circuitry determines the error condition exists, the link interface switches between the first configuration and the second configuration.
19. The controller device of claim 18 , wherein in the event that the error checking circuitry determines the error condition exists, the link interface switches from the first configuration to the second configuration.
20. The controller device of claim 15 , wherein the remedial action is to include re-transmitting command information, and command error detection information associated with the command information, to the solid state memory device.