Multi-die memory device
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
1. A memory device, comprising:
a logic integrated circuit (IC) base die, the logic IC base die including a primary interface for communicating with memory control circuitry, and multiple independent secondary interfaces; and
multiple memory die stacked on the logic IC base die, each of the multiple memory die including at least one independent memory interface coupled to a corresponding one of the multiple independent secondary interfaces of the logic IC base die in a dedicated manner using through-silicon-via (TSV) paths.
2. The memory device of claim 1 , wherein:
the primary interface comprises multiple serial signaling paths for transferring serialized signals between the memory control circuitry and the logic IC base die.
3. The memory device of claim 1 , wherein:
the multiple memory die comprise dynamic random access memory (DRAM) die.
4. The memory device of claim 1 , wherein each of the multiple memory die includes:
multiple storage arrays, each of the multiple storage arrays coupled to a corresponding one of the multiple independent secondary interfaces using a portion of the TSV paths.
5. The memory device of claim 4 , wherein:
the TSV paths define point-to-point connections between each of the multiple storage arrays and the corresponding ones of the multiple independent secondary interfaces.
6. The memory device of claim 1 , wherein:
the multiple independent secondary interfaces comprise configurable width interfaces that operate at a selectable first width or a selectable second width that is different than the first width.
7. The memory device of claim 6 , wherein:
a selection between the first width and the second width is based on a mode value.
8. The memory device of claim 7 , wherein:
the mode value is retrieved from storage.
9. A system in package (SiP), comprising:
a package substrate;
a processor IC chip disposed on the package substrate, the processor IC chip including memory control circuitry;
a memory device coupled to the processor IC chip, the memory device including
a logic integrated circuit (IC) base die, the logic IC base die including a primary interface for communicating with the memory control circuitry, and multiple independent secondary interfaces; and
multiple memory die stacked on the logic IC base die, each of the multiple memory die including at least one independent memory interface coupled to a corresponding one of the multiple independent secondary interfaces of the logic IC base die in a dedicated manner using through-silicon-via (TSV) paths.
10. The SiP of claim 9 , wherein:
the primary interface comprises multiple serial signaling paths for transferring serialized signals between the memory control circuitry of the processor IC chip and the logic IC base die.
11. The SiP of claim 9 , wherein:
the multiple memory die comprise dynamic random access memory (DRAM) die.
12. The SiP of claim 9 , wherein each of the multiple memory die includes:
multiple storage arrays, each of the multiple storage arrays coupled to a corresponding one of the multiple independent secondary interfaces using a portion of the TSV paths.
13. The SiP claim 9 , wherein:
the TSV paths define point-to-point connections between each of the multiple storage arrays and the corresponding ones of the multiple independent secondary interfaces.
14. The SiP of claim 9 , wherein:
the multiple independent secondary interfaces comprise configurable width interfaces that operate at a selectable first width or a selectable second width that is different than the first width.
15. The SiP of claim 14 , wherein:
a selection between the first width and the second width is based on a mode value.
16. A method of operation in a memory device, the method comprising:
communicating with a memory controller via a primary interface of a logic integrated circuit (IC) base die, the logic IC base die including multiple independent secondary interfaces; and
performing data transfers between the logic IC base die and multiple memory die stacked on the logic IC base die, the data transfers performed along TSV paths interconnected in a dedicated manner between at least one independent memory interface of each of the multiple memory die and a corresponding one of the multiple independent secondary interfaces of the logic IC base die.
17. The method according to claim 16 , wherein:
the communicating with the memory controller via the primary interface comprises transferring serialized signals along multiple serial signaling paths between the memory controller and the logic IC base die.
18. The method according to claim 16 , wherein:
the performing data transfers is carried out in accordance with a dynamic random access memory (DRAM) signaling protocol.
19. The method according to claim 16 , further comprising:
configuring the multiple independent secondary interfaces to operate at a selectable first width or a selectable second width that is different than the first width.
20. The method according to claim 19 , wherein:
the configuring of the multiple independent secondary interfaces to operate at a selectable first width or the second width is based on a mode value.