Integrated circuit that applies different data interface terminations during and after write data reception
In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.
1. An integrated circuit component comprising:
a data interface;
a command interface;
a chip-select input;
one or more programmable registers to store first and second termination control values; and
control circuitry to:
enable the command interface to receive a memory access command if a chip-select signal is asserted at the chip-select input during a first interval and, if the memory access command indicates a memory write operation, to:
transition a termination coupled to the data interface from a first impedance specified by the first control value to a second impedance specified by the second control value;
enable the data interface to receive write data during a write-data reception interval that transpires after the termination coupled to the data interface has transitioned to the second impedance; and
transition the termination coupled to the data interface from the second impedance to the first impedance after the write-data reception interval transpires; and
maintain the termination coupled to the data interface at the first impedance throughout a time period that would otherwise constitute the write-data reception interval if the chip-select signal is not asserted at the chip-select input during the first interval.
2. The integrated circuit component of claim 1 wherein the control circuitry to transition the termination coupled to the data interface from the first impedance to the second impedance comprises circuitry to transition the termination from the first impedance to the second impedance a predetermined time prior to reception of the write data via the data interface.
3. The integrated circuit component of claim 1 wherein the control circuitry to transition the termination coupled to the data interface from the first impedance to the second impedance comprises circuitry to transition the termination from the first impedance to the second impedance a predetermined time after reception of the command indicating the memory write operation.
4. The integrated circuit component of claim 1 wherein the control circuitry to transition the termination coupled to the data interface from the second impedance to the first impedance after the write-data reception interval transpires comprises circuitry to transition the termination from the second impedance to the first impedance a predetermined time after conclusion of the write-data reception interval.
5. The integrated circuit component of claim 1 wherein the data interface comprises a plurality of data input/output (I/O) nodes to be coupled to respective external data-signaling lines, and wherein the control circuitry to transition the termination to the second impedance comprises circuitry to switchably couple, to each of the plurality of data I/O nodes, a respective first plurality of termination load elements.
6. The integrated circuit component of claim 5 wherein the control circuitry to transition the termination to the first impedance comprises circuitry to switchably couple, to each of the plurality of data I/O nodes, a respective second plurality of termination load elements, the second plurality of termination load elements including at least one termination load element not included in the first plurality of termination load elements.
7. The integrated circuit component of claim 5 wherein the data interface comprises output drivers coupled respectively to the data I/O nodes, and wherein the circuitry to switchably couple the respective first plurality of termination load elements to each of the plurality of I/O nodes comprises circuitry to couple, to each of the plurality of I/O nodes, a plurality of pull-up elements and a plurality of pull-down elements within a respective one of the output drivers.
8. The integrated circuit component of claim 1 further comprising circuitry to write the first and second termination control values, after reception thereof via the command interface, into the one or more programmable registers for storage therein.
9. The integrated circuit component of claim 8 wherein the circuitry to write the first and second termination control values into the one or more programmable registers comprises circuitry to write the first and second termination control values into the one or more programmable registers in response to a register-write command received via the command interface, wherein at least one of the first and second termination control values is received via the command interface as part of the register-write command.
10. The integrated circuit component of claim 8 wherein the circuitry to write the first and second termination control values into the one or more programmable registers comprises circuitry to write, into the one or more programmable registers, first and second digital bit patterns indicative of the first and second impedances, respectively.
11. A method of operation within an integrated circuit component having a data interface, a command interface, a chip-select input, and one or more programmable registers, the method comprising:
storing first and second termination control values within the one or more programmable registers;
if a chip-select signal is asserted at the chip-select input during the first interval, receiving a command via the command interface;
if the command indicates a memory write operation:
transitioning a termination coupled to the data interface from a first impedance specified by the first control value to a second impedance specified by the second control value;
receiving write data via the data interface during a write-data reception interval that transpires after the termination coupled to the data interface has transitioned to the second impedance; and
after receiving the write data via the data interface, transitioning the termination coupled to the data interface from the second impedance to the first impedance; and
if the chip-select signal is not asserted at the chip-select input during the first interval, maintaining the termination coupled to the data interface at the first impedance throughout a time period that would otherwise constitute the write-data reception interval.
12. The method of claim 11 wherein transitioning the termination coupled to the data interface from the first impedance to the second impedance comprises transitioning the termination from the first impedance to the second impedance a predetermined time prior to reception of the write data via the data interface.
13. The method of claim 11 wherein transitioning the termination coupled to the data interface from the first impedance to the second impedance comprises transitioning the termination from the first impedance to the second impedance a predetermined time after reception of the command indicating the memory write operation.
14. The method of claim 11 wherein transitioning the termination coupled to the data interface from the second impedance to the first impedance comprises transitioning the termination from the second impedance to the first impedance a predetermined time after conclusion of the write-data reception interval.
15. The method of claim 11 wherein the data interface comprises a plurality of data input/output (I/O) nodes to be coupled to respective external data-signaling lines, and wherein transitioning the termination to the second impedance comprises coupling, to each of the plurality of data I/O nodes, a respective first plurality of termination load elements.
16. The method of claim 15 wherein transitioning the termination to the first impedance comprises coupling, to each of the plurality of data I/O nodes, a respective second plurality of termination load elements, the second plurality of termination load elements including at least one termination load element not included in the first plurality of termination load elements.
17. The method of claim 15 wherein the data interface comprises output drivers coupled respectively to the data I/O nodes, and wherein coupling the respective first plurality of termination load elements to each of the plurality of I/O nodes comprises coupling, to each of the plurality of I/O nodes, a plurality of pull-up elements and a plurality of pull-down elements within a respective one of the output drivers.
18. The method of claim 11 further comprising receiving the first and second termination control values via the command interface.
19. The method of claim 11 wherein storing first and second termination control values within the one or more programmable registers comprises storing first and second digital bit patterns indicative of the first and second impedances, respectively.
20. An integrated circuit component comprising:
a data interface;
a command interface;
a chip-select input;
means for storing first and second termination control values; and
means for:
enabling the command interface to receive a memory access command if a chip-select signal is asserted at the chip-select input during a first interval and, if the memory access command indicates a memory write operation, for:
transitioning a termination coupled to the data interface from a first impedance specified by the first control value to a second impedance specified by the second control value;
enabling the data interface to receive write data during a write-data reception interval that transpires after the termination coupled to the data interface has transitioned to the second impedance; and
transitioning the termination coupled to the data interface from the second impedance to the first impedance after the write-data reception interval transpires; and
maintaining the termination coupled to the data interface at the first impedance throughout a time period that would otherwise constitute the write-data reception interval if the chip-select signal is not asserted at the chip-select input during the first interval.