Integrated circuit that applies different data interface terminations during and after write data reception
In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.
1. An integrated circuit component comprising:
a command interface to receive commands;
a data interface to receive write data during a write-data reception interval;
first and second registers; and
control circuitry, responsive to one or more of the commands, to store within the first register and the second register, respectively:
a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and
a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.
2. The integrated circuit component of claim 1 wherein the command interface to receive commands comprises a command/address interface to receive, a predetermined time prior to the write-data reception interval and as one of the commands, a write command indicating that the write data is to be received via the data interface during the write-data reception interval.
3. The integrated circuit component of claim 2 wherein the control circuitry to store the first and second control values respectively within the first and second registers comprises termination control circuitry, responsive to the write command, to apply the first termination to the data interface during the write-data reception interval and to apply the second termination to the data interface after the write-data reception interval transpires.
4. The integrated circuit component of claim 3 wherein the termination control circuitry to apply the first termination to the data interface during the write-data reception interval in response to the write command comprises circuitry to apply the first termination to the data interface a predetermined time after receiving the write command.
5. The integrated circuit component of claim 1 wherein the data interface comprises a plurality of data input/output (I/O) nodes to be coupled to respective external data-signaling lines, and wherein the control circuitry to store the first and second control values respectively within the first and second registers comprises termination control circuitry to apply the first termination to the data interface during the write-data reception interval by coupling, to each of the plurality of data I/O nodes, a respective first plurality of termination load elements.
6. The integrated circuit component of claim 5 wherein the termination control circuitry applies the second termination to the data interface after the write-data reception interval transpires by coupling, to each of the plurality of data I/O nodes, a respective second plurality of termination load elements, each respective first plurality of termination load elements constituting a first load impedance and each respective second plurality of termination load elements constituting a second load impedance different from the first load impedance.
7. The integrated circuit component of claim 5 wherein the data interface comprises output drivers coupled respectively to the data I/O nodes, and wherein each respective first plurality of termination load elements comprises a plurality of pull-up elements and a plurality of pull-down elements within a respective one of the output drivers.
8. The integrated circuit component of claim 1 wherein the command interface is further to receive the first control value and the second control value.
9. The integrated circuit component of claim 8 wherein the first control value comprises a first digital bit pattern indicative of an impedance of the first termination and the second control value comprises a second digital bit pattern indicative of an impedance of the second termination, the second digital bit pattern being different from the first digital bit pattern.
10. The integrated circuit component of claim 1 wherein the first and second terminations comprise first and second impedance values, the first impedance value being higher than the second impedance value.
11. A method of operation within an integrated circuit component having a data interface to receive write data during a write-data reception interval, a command interface, a first register, and a second register, the method comprising:
receiving one or more register programming commands via the command interface; and
in response to receiving the one or more register programming commands, storing a first control value within the first register and a second control value within the second register, the first control value specifying a first termination to be applied to the data interface during the write-data reception interval and the second control value specifying a second termination to be applied to the data interface after the write-data reception interval transpires.
12. The method of claim 11 further comprising receiving via the command interface, a predetermined time prior to the write-data reception interval and as one of the commands, a write command indicating that the write data is to be received via the data interface during the write-data reception interval.
13. The method of claim 12 further comprising applying the first and second terminations to the data interface during and after the write-data reception interval, respectively, in response to receiving the write command.
14. The method of claim 13 wherein applying the first termination to the data interface during the write-data reception interval in response to receiving the write command comprises circuitry applying the first termination to the data interface a predetermined time after receiving the write command.
15. The method of claim 11 wherein the data interface comprises a plurality of data input/output (I/O) nodes to be coupled to respective external data-signaling lines, the method further comprising applying the first termination to the data interface during the write-data reception interval by coupling, to each of the plurality of data I/O nodes, a respective first plurality of termination load elements.
16. The method of claim 15 further comprising applying the second termination to the data interface after the write-data reception interval transpires by coupling, to each of the plurality of data I/O nodes, a respective second plurality of termination load elements, each respective first plurality of termination load elements constituting a first load impedance and each respective second plurality of termination load elements constituting a second load impedance different from the first load impedance.
17. The method of claim 15 wherein the data interface comprises output drivers coupled respectively to the data I/O nodes, and wherein coupling the respective first plurality of termination load elements to each of the plurality of I/O nodes comprises coupling, to each of the plurality of I/O nodes, a plurality of pull-up elements and a plurality of pull-down elements within a respective one of the output drivers.
18. The method of claim 11 further comprising receiving the first control value and the second control value via the command interface.
19. The method of claim 18 wherein receiving the first control value via the command interface comprises receiving a first digital bit pattern indicative of an impedance of the first termination and receiving the second control value via the command interface comprises receiving a second digital bit pattern indicative of an impedance of the second termination, the second digital bit pattern being different from the first digital bit pattern.
20. An integrated circuit component comprising:
a data interface to receive write data during a write-data reception interval;
a first register;
a second register;
means for receiving commands; and
means, responsive to one or more of the commands, for storing within the first register and the second register, respectively:
a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and
a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.