Transaction-based on-die termination
A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
1. A memory component comprising:
a memory core;
a control interface to receive commands and a select signal, the select signal indicating, for each of the commands, whether the memory component is a target of an operation specified by the command;
a data input/output (I/O); and
termination circuitry to:
terminate the data I/O with a first termination impedance in response to reception, via the control interface, of (i) a first command specifying a memory write operation and (ii) the select signal in a state indicating that the memory component is a target of the memory write operation;
terminate the data I/O with a second termination impedance after reception, via the data I/O, of write data to be stored within the memory core per the memory write operation; and
disable termination of the data I/O in response to reception, via the control interface, of (i) a second command indicating a memory read operation and (ii) the select signal in a state indicating that the memory component is a target of the memory read operation.
2. The memory component of claim 1 wherein the termination circuitry to terminate the data I/O with the first termination impedance comprises a variable impedance circuit, control circuitry to configure the variable impedance circuit to exhibit the first termination impedance, and switch circuitry to switchably couple the variable impedance circuit to the data I/O.
3. The memory component of claim 2 wherein the control circuitry to configure the variable impedance circuit to exhibit the first termination impedance comprises programmable storage circuitry having first storage elements to store a first digital value representative of the first termination impedance and circuitry to selectively convey impedance control signals corresponding to the first digital value to impedance control inputs of the variable impedance circuit.
4. The memory component of claim 3 wherein the circuitry to selectively convey impedance control signals corresponding to the first digital value to impedance control inputs of the variable impedance circuit comprises circuitry to convey the impedance control signals corresponding to the first digital value to the impedance control inputs of the variable impedance circuit in response to reception, via the control interface, of the first command specifying the memory write operation and the select signal having the state indicating that the memory component is a target of the memory write operation.
5. The memory component of claim 4 wherein the programmable storage circuitry additionally has second storage elements to store a second digital value representative of the second termination impedance and wherein the circuitry to selectively convey impedance control signals to the impedance control inputs of the variable impedance circuit comprises circuitry to convey impedance control signals corresponding to the second digital value to the impedance control inputs of the variable impedance circuit after reception, via the data I/O, of the write data to be stored within the memory core per the memory write operation.
6. The memory component of claim 2 wherein the termination circuitry to disable termination of the data I/O in response to reception of the second command indicating the memory read operation and the select signal in the state indicating that the memory component is a target of the memory read operation comprises circuitry configure the switch circuitry to decouple the variable impedance circuit from the data I/O.
7. The memory component of claim 1 further comprising an output driver coupled to the data I/O and having pull-up driver elements and pull-down driver elements, and wherein the termination circuitry to terminate the data I/O with the first termination impedance in response to reception of the first command and to terminate the data I/O with the second termination impedance after reception of the write data comprises circuitry to switchably couple a first subset of the pull-up driver elements and the pull-down driver elements to the data I/O to terminate the data I/O with the first termination impedance and to switchably couple a second subset of the pull-up driver elements and the pull-down driver elements to the data I/O to terminate the data I/O with the second termination impedance.
8. The memory component of claim 7 wherein the first subset of pull-up driver elements and pull-down driver elements includes at least one pull-up driver element and one pull-down driver element not included in the second subset of pull-up driver elements and pull-down driver elements.
9. The memory component of claim 1 wherein the termination circuitry additionally terminates the data I/O with the second termination impedance in response to detection of a third command at the control interface in conjunction with the select signal in a state indicating that the memory component is not a target of an operation specified by the third command.
10. The memory component of claim 1 wherein the control interface to receive commands and the select signal comprises:
one or more command inputs to receive, at respective times, signals representative of respective commands from one or more external command signaling lines; and
sampling circuitry to sample the signals received via the one or more command inputs at each of the respective times in response to indication by the select signal that the memory component is a target of a respective one of the commands represented by the signals received via the one or more command inputs.
11. A method of operation within a memory component having a memory core, the method comprising:
terminating a data input/output (I/O) with a first termination impedance in response to concurrent reception of a first command specifying a memory write operation and a select signal in a state indicating that the memory component is a target of the memory write operation;
terminating the data I/O with a second termination impedance after reception, via the data I/O, of write data to be stored within the memory core per the memory write operation; and
disabling termination of the data I/O in response to concurrent reception of a second command indicating a memory read operation and the select signal in a state indicating that the memory component is a target of the memory read operation.
12. The method of claim 11 wherein terminating the data I/O with the first termination impedance comprises configuring a variable impedance circuit to exhibit the first termination impedance and switchably coupling the variable impedance circuit to the data I/O.
13. The method of claim 12 wherein configuring the variable impedance circuit to exhibit the first termination impedance comprises storing a first digital value representative of the first termination impedance within a programmable storage circuit and switchably conveying impedance control signals corresponding to the first digital value to impedance control inputs of the variable impedance circuit.
14. The method claim 13 wherein switchably conveying impedance control signals corresponding to the first digital value to impedance control inputs of the variable impedance circuit comprises conveying the impedance control signals corresponding to the first digital value to the impedance control inputs of the variable impedance circuit in response to concurrent reception of the first command specifying the memory write operation and the select signal in the state indicating that the memory component is a target of the memory write operation.
15. The method of claim 14 wherein terminating the data I/O with the second termination impedance comprises configuring the variable impedance circuit to exhibit the second termination impedance, including:
storing a second digital value representative of the second termination impedance within the programmable storage circuit; and
switchably conveying impedance control signals corresponding to the second digital value to the impedance control inputs of the variable impedance circuit after reception, via the data I/O, of the write data to be stored within the memory core per the memory write operation.
16. The method of claim 12 wherein disabling termination of the data I/O comprises decoupling the variable impedance circuit from the data I/O.
17. The method of claim 11 wherein terminating the data I/O with the first termination impedance comprises switchably coupling to the data I/O a first subset of pull-up elements and pull-down elements within an output signal driver, and wherein terminating the data I/O with the second termination impedance comprises switchably coupling to the data I/O a second subset of the pull-up driver elements and pull-down driver elements within the output signal driver.
18. The method of claim 17 wherein the first subset of the pull-up driver elements and pull-down driver elements includes at least one pull-up driver element and one pull-down driver element not included in the second subset of the pull-up driver elements and pull-down driver elements.
19. The method of claim 11 wherein terminating the data input/output (I/O) with the first termination impedance in response to concurrent reception of a first command specifying a memory write operation and the select signal in a state indicating that the memory component is a target of the memory write operation comprises receiving the first command at a control interface of the memory component, the method further comprising terminating the data I/O with the second termination impedance in response to detecting a third command at the control interface in conjunction with the select signal in a state indicating that the memory component is not a target of an operation specified by the third command.
20. The method of claim 11 wherein terminating the data I/O with the first termination impedance in response to concurrent reception of the first command and the select signal having the state indicating that the memory component is a target of the memory write operation comprises:
receiving signals representative of the first command from one or more external command signaling lines; and
sampling the signals received from the one or more external command signaling lines to generate a digitized value corresponding to the first command in response to indication by the select signal that the memory component is a target of the memory write operation specified by the first command.
21. A dynamic random access memory integrated circuit (DRAM IC) comprising:
a control interface to receive commands and a select signal, the select signal indicating, for each of the commands, whether the DRAM IC is a target of an operation specified by the command;
a data input/output (I/O); and
termination circuitry to:
terminate the data I/O with a first termination impedance in response to reception, via the control interface, of (i) a first command specifying a memory write operation and (ii) the select signal in a state indicating that the memory component is a target of the memory write operation;
terminate the data I/O with a second termination impedance a predetermined time after reception of the first command;
disable termination of the data I/O in response to reception, via the control interface, of (i) a second command indicating a memory read operation and (ii) the select signal in a state indicating that the memory component is a target of the memory read operation; and
terminate the data I/O with the second termination impedance in response to detection of a third command at the control interface in conjunction with the select signal in a state indicating that the memory component is not a target of an operation specified by the third command.