Polarity driven dynamic on-die termination

1. An integrated circuit comprising:

an input/output (I/O) circuit to receive a command;

an on-die termination (ODT) pin to receive one or more ODT signals;

control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command, wherein the control logic includes

ODT activation logic to detect, during a first clock, an ODT activation signal on the ODT pin, and

ODT value selection logic to detect, during a second clock, an ODT value selection signal on the ODT pin and to select one of a first ODT value and a second ODT value based, at least in part, on the ODT value selection signal; and

a termination resistance circuit coupled with the control logic and the I/O circuit, the termination resistance circuit to dynamically provide one of a primary ODT resistance and a secondary ODT resistance for the I/O circuit.

2. The integrated circuit of claim 1 , wherein the ODT activation logic is further to decode the command and to determine a termination length based, at least in part, on the command.

3. The integrated circuit of claim 1 , further comprising:

a first register to contain the primary ODT value; and

a second register to contain the secondary ODT value.

4. The integrated circuit of claim 3 , wherein the ODT value selection logic is to

select the primary ODT value from the first register, if the ODT value selection signal is a logic one; and

select the secondary ODT value from the second register, if the ODT value selection signal is a logic zero.

5. The integrated circuit of claim 1 , wherein the command includes an associated burst length (BL) and further wherein the control logic to control the length of termination based, at least in part, on the command comprises:

control logic to determine the length of termination based, at least in part, on the burst length (BL).

6. The integrated circuit of claim 5 , wherein the control logic to determine the length of termination based, at least in part, on the burst length (BL) comprises:

control logic to determine the length of termination based, at least in part, on the expression (BL/M)+N.

7. The integrated circuit of claim 6 , wherein M and N equal two.

8. The integrated circuit of claim 1 , wherein the integrated circuit comprises a memory device.

9. A method comprising:

receiving, at a first clock, a command on an input/output (I/O) circuit of an integrated circuit;

receiving, at the first clock, an on-die termination (ODT) activation signal on an ODT pin of the integrated circuit;

receiving, at a second clock, an ODT value selection signal on the ODT pin of the integrated circuit;

determining a length of termination based, at least in part, on the command from the external controller; and

providing a termination resistance for the I/O circuit during a period substantially equal to the length of termination.

10. The method claim 9 , wherein the second clock is subsequent to the first clock.

11. The method claim 9 , further comprising:

selecting an ODT value responsive, at least in part, to receiving the ODT value selection signal.

12. The method of claim 11 , wherein selecting the ODT value responsive, at least in part, to receiving the ODT value selection signal comprises:

selecting a primary ODT value, if the ODT value selection signal is a logic one; and

selecting a secondary ODT value, if the ODT value selection signal is a logic zero.

13. The method of claim of claim 9 , wherein determining the length of termination based, at least in part, on the command from the external controller comprises:

decoding the command;

determining a burst length (BL) associated with the command; and

determining the length of termination based, at least in part, on the burst length associated with the command.

14. The method of claim 13 , wherein determining the length of termination based, at least in part, on the burst length associated with the command comprises:

determining the length of termination based, at least in part, on the expression (BL/M)+N.

15. The method of claim 14 , wherein M and N are each equal to two.

16. The method of claim 9 , wherein receiving, at the first clock, the ODT activation signal on an ODT pin of the integrated circuit further comprises:

preventing a reset of a state of the ODT activation signal for a predetermined period of time to allow for a time multiplexing of signals on the ODT pin.

17. A system comprising:

a first integrated circuit coupled to an interconnect; and

a second integrated circuit coupled to the first integrated circuit via the interconnect, the second integrated circuit including,

an input/output circuit to receive a command;

an on-die termination pin, and

control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and ODT value selection signal on the ODT pin, the control logic farther to control a length of termination based, at least in part, on the command, wherein the control logic includes

ODT activation logic to detect, during a first clock, an ODT activation signal on the ODT pin, and

ODT value selection logic to detect, during a second clock, an ODT value selection signal on the ODT pin and to select one of a primary ODT value and secondary ODT value based, at least in part, on the ODT value selection signal.

18. The system of claim 17 , wherein the control logic is to prevent a reset of a state of the ODT activation signal for a predetermined period of time to enable a time multiplexing of signals on the ODT pin.

19. The system of claim 17 , wherein the first integrated circuit comprises a memory controller.

20. The system of claim 17 , wherein the second integrated circuit comprises a memory device.

21. The system of claim 20 , wherein the memory device is a dynamic random access memory device.