Nonvolatile memory with command-driven on-die termination
On-die termination circuitry within a non-volatile memory device applies a first termination resistance to an I/O node in response to a data storage command indicating that a data signal conveyed on a bidirectional signaling line is to be received within the non-volatile memory device via the I/O node, and applies a second termination resistance to the I/O node in response to information indicating that another memory device is to output a data signal onto the bidirectional signaling line.
1. A non-volatile memory device comprising:
a signaling interface to receive, at respective times, data storage commands and data read commands, the signaling interface including at least one input/output (I/O) node to be coupled to a bidirectional signaling line; and
control circuitry to apply a first termination resistance to the I/O node in response to a first data storage command indicating that a data signal conveyed on the bidirectional signaling line is to be received within the non-volatile memory device via the I/O node, and to apply a second termination resistance to the I/O node in response to information indicating that another memory device is to output a data signal onto the bidirectional signaling line.
2. The non-volatile memory device of claim 1 wherein the information indicating that another memory device is to output a data signal comprises, at least in part, an address value received via the signaling interface and determined not to match an address of the non-volatile memory device.
3. The non-volatile memory device of claim 2 wherein the address value received via the signaling interface comprises an address value received in association with a data read command.
4. The non-volatile memory device of claim 1 wherein the first data storage command is received at least in part via the I/O node and wherein the information indicating that another memory device is to output a data signal is received at least in part via the I/O node.
5. The non-volatile memory device of claim 1 wherein the control circuitry decouples at least a portion of the first termination resistance and at least a portion of the second termination resistance from the I/O node while outputting a data signal onto the bidirectional signaling line in response to a data read command directed to the non-volatile memory device.
6. The non-volatile memory device of claim 1 wherein the signaling interface comprises an output driver to output a data signal onto the bidirectional signaling line via the I/O node in response to a read command that is (i) received via the signaling interface and (ii) directed to the non-volatile memory device, the control circuitry to apply no termination resistance to the I/O node during an interval in which the output driver is outputting the data signal onto the bidirectional signaling line.
7. The non-volatile memory device of claim 1 wherein the control circuitry to apply the second termination resistance to the I/O node in response to the information indicating that the other memory device is to output a data signal onto the bidirectional signaling line comprises circuitry to determine whether a chip-select signal is asserted or deasserted.
8. The non-volatile memory device of claim 1 further comprising a programmable register to store first and second control values that control resistance values of the first and second termination resistances, respectively.
9. The non-volatile memory device of claim 1 wherein the signaling interface to receive data storage commands receives a write enable signal indicative of a data storage operation.
10. A method of operation within a non-volatile memory device, the method comprising:
receiving via a signaling interface, at respective times, data storage commands and data read commands, the signaling interface including at least one input/output (I/O) node coupled to a bidirectional signaling line;
applying a first termination resistance to the I/O node in response to a first data storage command indicating that a data signal conveyed on the bidirectional signaling line is to be received within the non-volatile memory device via the I/O node; and
applying a second termination resistance to the I/O node in response to information indicating that another memory device is to output a data signal onto the bidirectional signaling line.
11. The method of claim 10 wherein the information indicating that another memory device is to output a data signal comprises, at least in part, an address value received via the signaling interface and determined not to match an address of the non-volatile memory device.
12. The method of claim 11 wherein the address value received via the signaling interface comprises an address value received in association with a data read command.
13. The method of claim 10 wherein the first data storage command indicating is received at least in part via the I/O node and the information indicating that another memory device is to output a data signal is received at least in part via the I/O node.
14. The method of claim 10 further comprising decoupling at least a portion of the first termination resistance and at least a portion of the second termination resistance from the I/O node while outputting a data signal onto the bidirectional signaling line in response to a data read command directed to the non-volatile memory device.
15. The method of claim 10 further comprising:
outputting a data signal onto the bidirectional signaling line via the I/O node in response to a read command that is (i) received via the signaling interface and (ii) directed to the non-volatile memory device; and
applying no termination resistance to the I/O node while outputting the data signal onto the bidirectional signaling line.
16. The method of claim 10 wherein applying the second termination resistance to the I/O node in response to information indicating that the other memory device is to output a data signal onto the bidirectional signaling line comprises determining whether a chip-select signal is asserted or deasserted.
17. The method of claim 10 further comprising storing first and second control values within a programmable register to control resistance values of the first and second termination resistances, respectively.
18. The method of claim 10 wherein receiving data storage commands via the signaling interface comprises receiving a write enable signal indicative of a data storage operation.
19. A non-transitory machine-readable medium that stores data representative of a non-volatile memory device comprising:
a signaling interface to receive, at respective times, data storage commands and data read commands, the signaling interface including at least one input/output (I/O) node to be coupled to a bidirectional signaling line; and
control circuitry to apply a first termination resistance to the I/O node in response to a data storage command indicating that a data signal conveyed on the bidirectional signaling line is to be received within the non-volatile memory device via the I/O node, and to apply a second termination resistance to the I/O node in response to information indicating that another memory device is to output a data signal onto the bidirectional signaling line.
20. A non-volatile memory device comprising:
a signaling interface to receive, at respective times, data storage commands and data read commands, the signaling interface including at least one input/output (I/O) node to be coupled to a bidirectional signaling line; and
means for applying a first termination resistance to the I/O node in response to a data storage command indicating that a data signal conveyed on the bidirectional signaling line is to be received within the non-volatile memory device via the I/O node, and for applying a second termination resistance to the I/O node in response to information indicating that another memory device is to output a data signal onto the bidirectional signaling line.