Memory controller with staggered request signal output

1. A method of operation within a memory controller, the method comprising:

generating a first timing signal having a phase offset relative to a first clock signal in accordance with a first programmed value;

generating a second timing signal having a phase offset relative to the first clock signal in accordance with a second programmed value; and

transmitting an address value in response to the first timing signal and a control value in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

2. The method of claim 1 wherein transmitting the address value in response to the first timing signal comprises outputting a plurality of address bits from the memory controller in parallel in response to a first transition of the first timing signal.

3. The method of claim 1 wherein transmitting the control value in response to the second timing signal comprises outputting a chip-select signal from the memory controller in response to a transition of the second timing signal, the chip-select signal to select a subset of memory devices to be accessed within a memory subsystem.

4. The method of claim 1 further comprising outputting the first clock signal from the memory controller, and wherein transmitting the control value in response to the second timing signal comprises outputting a clock enable signal from the memory controller in response to a transition of the second timing signal, the clock-enable signal to enable a subset of memory devices within a memory subsystem to receive the first clock signal.

5. The method of claim 1 wherein transmitting the control value in response to the second timing signal comprises outputting a termination control signal from the memory controller in response to a transition of the second timing signal, the termination control signal to switchably couple a subset of termination structures within a memory subsystem to data lines extending between the memory controller and the memory subsystem.

6. The method of claim 5 wherein the subset of termination structures are disposed within a subset of integrated-circuit memory devices of the memory subsystem.

7. The method of claim 1 further comprising transmitting a command value in response to the first timing signal, the command constituting an additional portion of the first memory access request and indicating whether the memory access request is a memory read request or a memory write request.

8. The method of claim 1 wherein generating a first timing signal having a phase offset in accordance with a first programmed value comprises:

generating a plurality of sub-phase clock signals that are distributed in phase over the period of the first clock signal;

selecting a pair of the sub-phase clock signals that bound a phase range indicated by the first programmed value; and

interpolating between the selected pair of sub-phase clock signals in accordance with the first programmed value.

9. The method of claim 1 wherein generating a first timing signal having a phase offset in accordance with a first programmed value comprises:

generating a plurality of sub-phase clock signals that have respective phase offsets relative to the first clock signal; and

switchably coupling, in response the first programmed value, one of the sub-phase clock signals onto a signal line as the first timing signal.

10. The method of claim 1 further comprising storing the first and second programmed values in first and second storage locations, respectively, within the memory controller in response to one or more instructions from a host device.

11. The method of claim 10 wherein the first and second storage locations each comprise a respective plurality of storage elements of a programmable register within the memory controller.