Controller that receives a cyclic redundancy check (CRC) code from an electrically erasable programmable memory device
A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
1. A memory controller device to control the operation of an electrically erasable programmable memory chip having a solid-state memory core, the controller device comprising:
a circuit to transmit a command to the electrically erasable programmable memory chip, the command instructing the memory chip to provide a group of data bits, accessed from the solid-state memory core, along with a first cyclic redundancy check (CRC) code to the memory controller via a common link;
a receive circuit to receive, the group of data bits and the first CRC code, wherein the group of data bits is time multiplexed with the first CRC code over the common link;
an encoder to generate a second CRC code from the received group of data bits; and
a circuit to compare the first CRC code with the second CRC code and signal an error condition in the event that the comparison between the first CRC code and the second CRC code indicates an error, wherein, in the event of the error condition, the memory controller is to instruct the memory chip to transmit a second instance of the group of data bits and first CRC code to the memory controller, via the common link.
2. The memory controller device of claim 1 , wherein, in the event of the error, the memory controller initiates a remedial action that includes the instructing of the memory chip to transmit the second instance of the group of data bits and first CRC code to the memory controller, via the common link.
3. The memory controller of claim 2 , wherein the remedial action includes transmitting retry information to the memory chip using a command link.
4. The memory controller device of claim 1 , wherein instructing the memory chip to transmit the second instance of the group of data bits and first CRC code via the link includes sending a command with error protection provided by an error correction code.
5. The memory controller device of claim 4 , wherein the command with error protection is transmitted using a format of one symbol per clock cycle of a clock signal.
6. The memory controller device of claim 1 , further comprising a transmitter circuit to transmit write data and a third CRC code to the memory chip.
7. The memory controller device of claim 6 , wherein the memory chip is to transmit a retry indicator to the memory controller when an error is detected in the write data, the memory controller to re-transmit the write data and third CRC code to the memory chip upon receipt of the retry indicator.
8. The memory controller device of claim 1 , wherein a serial-to-parallel conversion is to be performed on the group of data bits and first CRC code received via the receive circuit.
9. A method of operation of a memory controller device, the memory controller device to control operation of an electrically erasable programmable memory chip having a solid-state memory core, the method comprising:
transmitting a command to the electrically erasable programmable memory chip, the command instructing the memory chip to provide a group of data bits, accessed from the solid-state memory core, along with a first cyclic redundancy check (CRC) code to the memory controller via a common link;
receiving the group of data bits and the first CRC code, wherein the group of data bits is time multiplexed with the first CRC code over the common link;
generating a second CRC code from the received group of data bits;
comparing the first CRC code with the second CRC code and signal an error condition in the event that the comparison between the first CRC code and the second CRC code indicates an error;
instructing the memory chip to transmit a second instance of the group of data bits and first CRC code to the memory controller, via the common link, in the event of the error condition.
10. The method of claim 9 , wherein, in the event of the error, the memory controller initiates a remedial action that includes the instructing of the memory chip to transmit the second instance of the group of data bits and first CRC code to the memory controller, via the common link.
11. The method of claim 10 , wherein the remedial action includes transmitting retry information to the memory chip using a command link.
12. The method of claim 9 , wherein instructing the memory chip to transmit the second instance of the group of data bits and first CRC code via the link includes sending a command with error protection provided by an error correction code.
13. The method of claim 12 , wherein the command with error protection is transmitted using a format of one symbol per clock cycle of a clock signal.
14. The method of claim 9 , further comprising transmitting write data and a third CRC code to the memory chip.
15. The method of claim 14 , wherein the memory chip is to transmit a retry indicator to the memory controller when an error is detected in the write data, the method further comprising re-transmitting the write data and third CRC code to the memory chip upon receipt of the retry indicator.
16. The method of claim 9 further comprising performing a serial-to-parallel conversion on the group of data bits and first CRC code received via the receive circuit.
17. A memory controller device, comprising:
means for transmitting a command to an electrically erasable programmable memory chip having a solid-state memory core, the command instructing the memory chip to provide a group of data bits, accessed from the solid-state memory core, along with a first cyclic redundancy check (CRC) code to the memory controller via a common link;
means for receiving the group of data bits and the first CRC code, wherein the group of data bits is time multiplexed with the first CRC code over the common link;
means for generating a second CRC code from the received group of data bits;
means for comparing the first CRC code with the second CRC code and signal an error condition in the event that the comparison between the first CRC code and the second CRC code indicates an error, wherein the memory controller is to instruct the memory chip to transmit a second instance of the group of data bits and first CRC code to the memory controller, via the common link, in the event of the error condition.
18. The memory controller device of claim 17 , wherein, in the event of the error, the memory controller initiates a remedial action that includes the instructing of the memory chip to transmit the second instance of the group of data bits and first CRC code to the memory controller, via the common link.
19. The memory controller of claim 18 , wherein the remedial action includes transmitting retry information to the memory chip using a command link.
20. The memory controller device of claim 17 , wherein instructing the memory chip to transmit the second instance of the group of data bits and first CRC code via the link includes sending a command with error protection provided by an error correction code.