Memory device with programmed device address and on-die-termination
An identifier value stored within a programmable register of a memory device is compared with a selector address received, together with a memory access command, via a signaling interface having at least one I/O node coupled to a bidirectional signaling line. On-die termination circuitry is transitioned between first and second states or maintained in one or the other of the first and second states based, at least in part, on whether the selector address matches the identifier value, with transition to the first state including switchably coupling a first termination resistance between the I/O node and a supply voltage line.
1. A non-volatile memory device comprising:
programmable register circuitry to store an identifier value that distinguishes the non-volatile memory device from one or more other non-volatile memory devices within a memory system;
a signaling interface to receive a selector address in association with a memory access command, the signaling interface including at least one input/output (I/O) node to be coupled to a bidirectional signaling line;
on-die termination circuitry coupled to the I/O node and configurable in any one of a plurality of states, including a first state and a second state, wherein in the first state, a first termination resistance is switchably coupled between the I/O node and a supply voltage line; and
control circuitry to compare the selector address with the identifier value and, based at least in part on whether the selector address matches the identifier value, to (i) transition the on-die termination circuitry from one of the first and second states to the other or (ii) maintain the on-die termination circuitry in one or the other of the first and second states.
2. The non-volatile memory device of claim 1 wherein, in the second state of the on-die termination circuitry, the first termination resistance is switchably decoupled from at least one of the I/O node or the supply voltage line.
3. The non-volatile memory device of claim 1 wherein the plurality of states in which the on-die termination circuitry is configurable includes a third state in which a second termination resistance is switchably coupled between the I/O node and the supply voltage line, and wherein, in the second state of the on-die termination circuitry, the first termination resistance is switchably decoupled from at least one of the I/O node or the supply voltage line, and the second termination resistance is switchably decoupled from at least one of the I/O node or the supply voltage line.
4. The non-volatile memory device of claim 3 wherein the control circuitry to transition the on-die termination circuitry from one of the first and second states to the other comprises circuitry to configure the on-die termination circuity in the first state, the second state or the third state based at least in part on whether the memory access command specifies a data storage operation or a data read operation, and based at least in part on whether the selector address matches the identifier value.
5. The non-volatile memory device of claim 4 wherein the circuitry to configure the on-die termination circuitry in the first state, the second state or the third state comprises circuitry to configure the on-die termination circuitry in (i) the first state if the selector address matches the identifier value and the memory access command specifies a data storage operation, (ii) the second state if the selector address matches the identifier value and the memory access command specifies a data read operation, and (iii) the third state if the selector address does not match the identifier value and the memory access command specifies a data read operation.
6. The non-volatile memory device of claim 3 wherein the programmable register circuitry includes respective storage fields to store first and second control values to control respective resistance values of the first and second termination resistances.
7. The non-volatile memory device of claim 1 further comprising circuitry to receive the identifier value and a corresponding programming command via the signaling interface and to store the identifier value within the programmable register circuitry in response to the programming command.
8. The non-volatile memory device of claim 1 wherein the signaling interface to receive the selector address comprises a plurality of signal receivers to receive respective address bits that constitute the selector address.
9. The non-volatile memory device of claim 8 wherein the plurality of signal receivers to receive respective address bits that constitute the selector address comprises at least one signal receiver coupled to receive a respective one of the address bits via the I/O node.
10. The non-volatile memory device of claim 1 further comprising a circuitry to receive the selector address in response to an incoming chip select signal.
11. A method of operation within a memory device having on-die termination circuitry configurable in any one of a plurality of states, the method of operation comprising:
storing, within programmable register circuitry of the memory device, an identifier value that distinguishes the memory device from one or more other memory devices within a memory system;
receiving a selector address and associated memory access command via a signaling interface having at least one input/output (I/O) node coupled to a bidirectional signaling line and to the on-die termination circuitry;
comparing the selector address with the stored identifier value; and
transitioning on-die termination circuitry between a first state and a second state or maintaining the on-die termination circuitry in the first state or the second state based, at least in part, on whether the selector address matches the identifier value, wherein transitioning the on-die termination circuitry to the first state includes switchably coupling a first termination resistance between the I/O node and a supply voltage line.
12. The method of claim 11 wherein, in the second state of the on-die termination circuitry, the first termination resistance is switchably decoupled from at least one of the I/O node or the supply voltage line.
13. The method of claim 11 wherein the on-die termination circuitry may be transitioned to a third state in which a second termination resistance is switchably coupled between the I/O node and the supply voltage line, and wherein, in the second state of the on-die termination circuitry, the first termination resistance is switchably decoupled from at least one of the I/O node or the supply voltage line, and the second termination resistance is also switchably decoupled from at least one of the I/O node or the supply voltage line.
14. The method of claim 13 further comprising configuring the on-die termination circuitry in the first state, the second state or the third state based at least in part on whether the memory access command specifies a data storage operation or a data read operation, and based at least in part on whether the selector address matches the identifier value.
15. The method of claim 14 wherein configuring the on-die termination circuitry in the first state, the second state or the third state comprises configuring the on-die termination circuitry in (i) the first state if the selector address matches the identifier value and the memory access command specifies a data storage operation, (ii) the second state if the selector address matches the identifier value and the memory access command specifies a data read operation, and (iii) the third state if the selector address does not match the identifier value and the memory access command specifies a data read operation.
16. The method of claim 13 further comprising storing, within the programmable register circuitry, first and second control values that control respective resistance values of the first and second termination resistances within the on-die termination circuitry.
17. The method of claim 11 further comprising receiving the identifier value and a corresponding programming command via the signaling interface and storing the identifier value within the programmable register circuitry in response to the programming command.
18. The method of claim 11 wherein receiving the selector address comprises receiving a plurality of address bits that constitute the selector address.
19. The method of claim 18 wherein receiving the plurality of address bits that constitute the selector address comprises receiving at least one of the address bits via the I/O node.
20. The method of claim 11 further comprising detecting assertion of a chip-select signal and, in response to detecting assertion of the chip-select signal, enabling the signaling interface to receive the selector address.
21. A non-transitory machine-readable medium that stores data representative of a non-volatile memory device comprising:
programmable register circuitry to store an identifier value that distinguishes the non-volatile memory device from one or more other non-volatile memory devices within a memory system;
a signaling interface to receive a selector address in association with a memory access command, the signaling interface including at least one input/output (I/O) node to be coupled to a bidirectional signaling line;
on-die termination circuitry coupled to the I/O node and configurable in any one of a plurality of states, including a first state in which a first termination resistance is switchably coupled between the I/O node and a supply voltage line; and
control circuitry to compare the selector address with the identifier value, and to configure the on-die termination circuitry in the first state or a second state of the plurality of states based, at least in part, on whether the selector address matches the identifier value.
22. A memory device comprising:
means for storing an identifier value that distinguishes the non-volatile memory device from one or more other non-volatile memory devices within a memory system;
means for receiving a selector address in association with a memory access command, the signaling interface including at least one input/output (I/O) node to be coupled to a bidirectional signaling line;
I/O terminating means configurable in any one of a plurality of states, including a first state in which a first termination resistance is switchably coupled between the I/O node and a supply voltage line; and
means for comparing the selector address with the identifier value, and for configuring the I/O terminating means in the first state or a second state of the plurality of states based, at least in part, on whether the selector address matches the identifier value.